SPI/I2C UART with 128-Word FIFOs Crystal Oscillator Set CLKSource[4]: ClockEn to" />
參數(shù)資料
型號: MAX3107EVKIT+
廠商: Maxim Integrated Products
文件頁數(shù): 9/52頁
文件大?。?/td> 0K
描述: EVAL KIT I2C/SPI UART MAX3107
產(chǎn)品培訓(xùn)模塊: Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,UART
已用 IC / 零件: MAX3107
主要屬性: 圖形用戶界面(GUI)
次要屬性: I²C & SPI 接口
已供物品: 板,線纜
SPI/I2C UART with 128-Word FIFOs
Crystal Oscillator
Set CLKSource[4]: ClockEn to 1 and CLKSource[1]:
CrystalEn to 1 to enable and select the crystal oscilla-
tor. The on-chip crystal oscillator has load capacitances
of 20pF integrated in both XIN and XOUT. Connect an
external crystal or ceramic oscillator between XIN and
XOUT.
External Clock Source
When an external clock signal is used, this should
be connected to XIN. Leave XOUT unconnected.
Set CLKSource[4]: ClockEn to 1 and CLKSource[1]:
CrystalEn to 0 to select external clocking.
PLL and Predivider
The internal predivider and PLL allow for a wide range
of external clock frequencies and baud rates. The PLL
can be configured to multiply the input clock rate by a
factor of 6, 48, 96, or 144 through PLLConfig[7:6]. The
predivider, located between the input clock and the PLL,
allows division of the input clock by a factor between 1
and 63 by writing to PLLConfig[5:0]. See the PLLConfig
register description for more information.
Fractional Baud-Rate Generator
The internal fractional baud-rate generator provides a
high degree of flexibility and high resolution in baud-
rate programming. The baud-rate generator has a 16-bit
integer divisor and a 4-bit word for the fractional divisor.
The fractional baud-rate generator can be used with the
external crystal or clock source.
The integer and fractional divisors are calculated through
the divisor, D:
REF
f
D
16 BaudRate
=
×
where fREF is the reference frequency input to the baud-
rate generator and D is the ideal divisor. fREF must be
less than 96MHz. In 2x and 4x rate modes, replace the
divisor 16 by 8 or 4, respectively.
The integer divisor portion, DIV, of the divisor, D, is
obtained by truncating D:
DIV = TRUNC(D)
Figure 6. Receive FIFO
Figure 7. Clock Selection Diagram
RECEIVE FIFO
FIFOTrgLvl[7:4]
TRIGGER
ISR[3]
WORD
ERROR 128
RxFIFOLvl
4
3
2
1
TIMEOUT
EMPTY
ERRORS
OVERRUN
LSR[1]
RECEIVED
DATA
RHR
RECEIVER
RX
I2C/SPI INTERFACE
LSR[0]
ISR[6]
LSR[5:2]
CURRENT FILL LEVEL
CRYSTAL
OSCILLATOR
XOUT
CrystalEn
XIN
BAUD-RATE
GENERATOR
ClockEn
PLLByps
PLLEn
PLL
DIVIDER
Maxim Integrated
17
MAX3107
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