參數(shù)資料
型號(hào)： MAX148
廠商： Maxim Integrated Products, Inc.
英文描述： +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs(8通道，133ksps，串行10位A/D轉(zhuǎn)換器)
中文描述： +2.7V至+5.25V、低功耗、8通道、串行10位ADC
文件頁(yè)數(shù)： 8/20頁(yè)
文件大小： 200K
代理商： MAX148
M
+2.7V, Low-Power, 8-Channel,
S erial 10-Bit ADC
8
_______________________________________________________________________________________
0.1μF
V
DD
DGND
AGND
COM
CS
SCLK
DIN
DOUT
SSTRB
SHDN
+3V
N.C.
0.01μF
CH7
VREF
C1
0.1
μ
F
0V TO
+2.500V
ANALOG
INPUT
OSCILLOSCOPE
CH1
CH2
CH3
CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
MAX148
+3V
2MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
2.5V
1000pF
COMP
V
OUT
+3V
MAX872
Figure 5. Quick-Look Circuit
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protec tion
Internal protection diodes, which clamp the analog
input to V
DD
and AGND, allow the channel input pins to
swing from AGND - 0.3V to V
DD
+ 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed V
DD
by more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on channel.
Quic k Look
To quickly evaluate the MAX148’s analog performance,
use the circuit of Figure 5. The MAX148 requires a control
byte to be written to DIN before each conversion. Tying
DIN to +3V feeds in control bytes of $FF (HEX), which
trigger single-ended unipolar conversions on CH7 in
external clock mode without powering down between
conversions. In external clock mode, the SSTRB output
pulses high for one clock period before the most signifi-
cant bit of the conversion result is shifted out of DOUT.
Varying the analog input to CH7 will alter the sequence
of bits from DOUT. A total of 15 clock cycles is required
per conversion. All transitions of the SSTRB and DOUT
outputs occur on the falling edge of SCLK.
How to S tart a Conversion
A conversion is started by clocking a control byte into
DIN. With
CS
low, each rising edge on SCLK clocks a
bit from DIN into the MAX148’s internal shift register.
After
CS
falls, the first arriving logic “1” bit defines the
MSB of the control byte. Until this first “start” bit arrives,
any number of logic “0” bits can be clocked into DIN
with no effect. Table 1 shows the control-byte format.
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