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參數(shù)資料
| 型號： | MAX148 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs(8通道，133ksps，串行10位A/D轉(zhuǎn)換器) |
| 中文描述： | +2.7V至+5.25V、低功耗、8通道、串行10位ADC |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | MAX148 |
M
+2.7V, Low-Power, 8-Channel,
S erial 10-Bit ADC
10
______________________________________________________________________________________
The MAX148 is compatible with Microwire, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. Microwire, SPI, and QSPI all
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the con-
version result). See Figure 17 for MAX148 QSPI connec-
tions.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS
low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 HEX) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 HEX) and, simulta-
neously, receive byte RB3.
6) Pull
CS
high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero, two sub-LSB bits, and
three trailing zeros. The total conversion time is a func-
tion of the serial clock frequency and the amount of idle
time between 8-bit transfers. Make sure that the total
conversion time does not exceed 120μs, to avoid
excessive T/H droop.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar inputs, the output is twos-com-
plement (Figure 15). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Cloc k Modes
The MAX148 may use either an external serial clock or
the internal clock to perform the successive-approxima-
tion conversion. In both clock modes, the external clock
shifts data in and out of the MAX148. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7–10 show the
timing characteristics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (Figure 6).
SSTRB and DOUT go into a high-impedance state when
CS
goes high; after the next
CS
falling edge, SSTRB will
output a logic low. Figure 8 shows the SSTRB timing in
external clock mode.
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
16
20
24
START
SEL2 SEL1 SEL0BIP
DIF
PD1 PD0
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
S1
S0
ACQUISITION
(CLK = 2MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
t
ACQ
A/D STATE
RB1
RB2
RB3
1.
Figure 6. 24-Bit External-Clock-Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with f
CLK
≤
2MHz).
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