參數(shù)資料
型號(hào): MAX148
廠商: Maxim Integrated Products, Inc.
英文描述: +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs(8通道,133ksps,串行10位A/D轉(zhuǎn)換器)
中文描述: +2.7V至+5.25V、低功耗、8通道、串行10位ADC
文件頁(yè)數(shù): 14/20頁(yè)
文件大小: 200K
代理商: MAX148
M
+2.7V, Low-Power, 8-Channel,
S erial 10-Bit ADC
14
______________________________________________________________________________________
__________ Applic ations Information
Power-On Reset
When power is first applied, and if
SHDN
is not pulled
low, internal power-on reset circuitry will activate the
MAX148 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have been sta-
bilized, the internal reset time is 10μs, and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if
CS
is low, the first logical 1 on
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT will shift out zeros.
Power-Down
The MAX148’s automatic power-down mode can save
considerable power when operating at speeds below
the maximum sampling rate.
Figure 13 shows the average supply current as a func-
tion of the sampling rate. You can save power by plac-
ing the converter in a low-current shutdown state
between conversions.
Select power-down via bits 1 and 0 of the DIN control
byte with
SHDN
high (Tables 1 and 4). Pull
SHDN
low at
any time to shut down the converter completely.
SHDN
overrides bits 1 and 0 of the control byte (Table 6).
Power-down mode turns off all chip functions that draw
quiescent current, reducing I
DD
typically to 1.2μA.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
POWERED UP
HARDWARE
POWER-
DOWN
POWERED UP
POWERED UP
10+2 DATA BITS
10+2 DATA BITS
INVALID
DATA
VALID
ATA
EXTERNAL
EXTERNAL
S X X X X X 1 1
S
0 0
X
X
X
X
X
X X X X X
S
1 1
SOFTWARE
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS SOFTWARE
POWER-DOWN
POWER-DOWN
POWERED UP
POWERED UP
DATA VALID
DATA VALID
INTERNAL
S X X X X X 1 0
S
0 0
X
X
X
X
X
S
MODE
DOUT
DIN
CLOCK
MODE
SETS INTERNAL
CLOCK MODE
SETS
POWER-DOWN
CONVERSION
CONVERSION
SSTRB
Figure 12a. Timing Diagram Power-Down Modes, External Clock
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
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