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參數(shù)資料
| 型號： | MAX148 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs(8通道，133ksps，串行10位A/D轉(zhuǎn)換器) |
| 中文描述： | +2.7V至+5.25V、低功耗、8通道、串行10位ADC |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 200K |
| 代理商： | MAX148 |
M
+2.7V, Low-Power, 8-Channel,
S erial 10-Bit ADC
______________________________________________________________________________________
13
SCLK
DIN
DOUT
CS
S
CONTROL BYTE 0
CONTROL BYTE 1
S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
SSTRB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONTROL BYTE 2
S
1
8
1
8
1
CS
SCLK
DIN
DOUT
S
CONTROL BYTE 0
CONTROL BYTE 1
S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
B9 B8 B7 B6
CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Data Framing
The falling edge of
CS
does
not
start a conversion on
the MAX148. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0
bit) is clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with
CS
low any
time the converter is idle; e.g., after V
DD
is applied.
OR
The first high bit clocked into DIN after bit 3 (B3) of a
conversion in progress is clocked onto the DOUT
pin.
If
CS
is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is terminated
and a new one started.
The fastest the MAX148 can run is 15 clocks per conver-
sion. Figure 11a shows the serial-interface timing neces-
sary to perform a conversion every 15 SCLK cycles in
external clock mode.
Most microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can drive
the MAX148. Figure 11b shows the serial-interface timing
necessary to perform a conversion every 16 SCLK cycles
in external clock mode.
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