參數(shù)資料
型號： MAX148
廠商： Maxim Integrated Products, Inc.
英文描述： +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs(8通道，133ksps，串行10位A/D轉(zhuǎn)換器)
中文描述： +2.7V至+5.25V、低功耗、8通道、串行10位ADC
文件頁數(shù)： 4/20頁
文件大?。?/td> 200K
代理商： MAX148
M
+2.7V, Low-Power, 8-Channel,
S erial 10-Bit ADC
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +3.6V, COM= 0V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1:
Tested at V
DD
= +2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
External reference (VREF = +2.500V), offset nulled.
Note 4:
Ground “on” channel; sine wave applied to all “off” channels.
Note 5:
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7:
Guaranteed by design. Not subject to production testing.
Note 8:
ADC performance is limited by the converter’s noise floor, typically 300μVp-p.
Note 9:
Electrical Characteristics are guaranteed from 2.7V to 3.6V. For operation beyond this range, see the Typical Operating
Characteristics. For guaranteed specifications beyond 2.7V to 3.6V, contact the factory.
Note 10:
Measured as
|
V
FS
(2.7V) - V
FS
(3.6V)
|
.
DIN to SCLK Setup
DIN to SCLK Hold
ns
ns
240
t
STR
t
SCK
CS
Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
ns
240
t
SDV
CS
Fall to SSTRB Output Enable
240
t
SSTRB
SCLK Fall to SSTRB
ns
ns
ns
ns
0
CS
to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
ns
100
t
CSS
t
CSH
t
CH
t
CL
CS
to SCLK Rise Setup
ns
240
t
TR
CS
Rise to Output Disable
ns
240
t
DV
CS
Fall to Output Enable
20
20
200
240
t
DO
SCLK Fall to Output Data Valid
ns
0
t
DH
μs
ns
1.5
100
t
ACQ
t
DS
Acquisition Time
0
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
Figure 1
Figure 2, C
LOAD
= 50pF
Figure 1, C
LOAD
= 50pF
MAX148_C/E
MAX148_M
CONDITIONS
ns
Figure 1, C
LOAD
= 50pF
200
200
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