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參數(shù)資料
| 型號(hào)： | MAX148 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs(8通道，133ksps，串行10位A/D轉(zhuǎn)換器) |
| 中文描述： | +2.7V至+5.25V、低功耗、8通道、串行10位ADC |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 200K |
| 代理商： | MAX148 |
M
+2.7V, Low-Power, 8-Channel,
S erial 10-Bit ADC
6
_______________________________________________________________________________________
_______________Detailed Desc ription
The MAX148 analog-to-digital converter (ADC) uses a
successive-approximation conversion technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 10-bit digital output. A flexible serial interface
provides easy interface to microprocessors (μPs). No
external hold capacitors are required. Figure 3 shows
the block diagram for the MAX148.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog compara-
tor is illustrated in the equivalent input circuit (Figure 4). In
single-ended mode, IN+ is internally switched to
CH0–CH7, and IN- is switched to COM. In differential
mode, IN+ and IN- are selected from the following pairs:
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1μF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
HOLD
. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on C
HOLD
as a sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching C
HOLD
from the positive input (IN+) to the neg-
ative input (IN-). In single-ended mode, IN- is simply
COM. This unbalances node ZERO at the input of the
comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
9
COM
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
PIN
10
SHDN
Three-Level Shutdown Input. Pulling
SHDN
low shuts the MAX148 down to 10μA (max) supply current;
otherwise the MAX148 is fully operational. Letting
SHDN
float sets the internal clock frequency to 1.8MHz.
Pulling
SHDN
high sets the internal clock frequency to 225kHz. See Hardware Power-Downsection.
11
VREF
External Reference Voltage Input for analog-to-digital conversion.
15
DOUT
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when
CS
is high.
14
DGND
Digital Ground
13
AGND
Analog Ground
12, 20
V
DD
Positive Supply Voltage
19
SCLK
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
18
CS
Active-Low Chip Select. Data will not be clocked into DIN unless
CS
is low. When
CS
is high, DOUT is
high impedance.
17
DIN
Serial Data Input. Data is clocked in at the rising edge of SCLK.
16
SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX148 begins the A/D con-
version and goes high when the conversion is done. In external clock mode, SSTRB pulses high for
one clock period before the MSB decision. High impedance when
CS
is high (external clock mode).
______________________________________________________________Pin Desc ription
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