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| 型號： | M38C24M4A-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 99/102頁 |
| 文件大小： | 1369K |
| 代理商： | M38C24M4A-XXXFP |
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Rev.2.00
May 28, 2004
page 96 of 100
38C2 Group (A Version)
3. Read order to timer X
In all modes, read the following registers in the order as shown
below;
the timer X register (extension),
the timer X register (high-order),
the timer X register (low-order).
When reading the timer X register (extension) is not required, read
the timer X register (high-order) first and the timer X register (low-
order). Read order to the compare register is not specified.
If reading to the timer X register during write operation or writing to
it during read operation is performed, normal operation will not be
performed.
4. Write to timer X
Which write control can be selected by the timer X write control bit
(b3) of the timer X mode register (address 002F16), writing data to
both the latch and the timer at the same time or writing data only to
the latch. When writing a value to the timer X address to write to the
latch only, the value is set into the reload latch and the timer is
updated at the next underflow. After reset release, when writing a
value to the timer X address, the value is set into the timer and the
timer latch at the same time, because they are written at the same
time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this
time, counting is stopped during writing to the high-order reload
latch.
Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
5. Set of timer X mode register
Set the write control bit of the timer X mode register to “1” (write to
the latch only) when setting the IGBT output and PWM modes.
Output waveform simultaneously reflects the contents of both regis-
ters at the next underflow after writing to the timer X register (high-
order).
6. When selecting timer X pulse width measurement mode
When selecting the timer X pulse width measurement mode, enable
(set “0”) data for the event couter window control (bit 5 of timer X
mode register (address 002F16)).
<Reason>
When data for the event counter window control is set to “1” (dis-
abled), the CNTR0 input is not accepted after timer 1 underflow be-
cause this bit controls the CNTR0 input.
7. IGBT output mode
Do not write “1” to the timer X register (extension) when using the
IGBT output mode.
When using the IGBT output mode, set the port sharing the INT0 pin
to input mode and set the port sharing the TXOUT pin to output mode.
When using the output control function (INT1, INT2), set the port
sharing the INT1, INT2 pin to input mode.
When using the output control function (INT1 and INT2) in the IGBT
output mode, set the levels of INT1 and INT2 to “H” in the falling
edge active or to “L” in the rising edge active before switching to the
IGBT output mode. Set the level of INT0 to “H” in the falling edge
active or to “L” in the rising edge active before switching to the IGBT
output mode.
When setting the timer X output control bit 1 or 2 (bit 3 or 4 of timer
X control register (address 0FF416)) to “1” and initializing the output
of the TXOUT pin by interrupt signal of INT1 or INT2, while the output
level from the TXOUT pin changes after setting the timer X output
control bit 1 or 2 to “1”, the following delay will occur.
Minimum: Analog delay
Maximum: Timer X count source 1 cycle + Analog delay
In the following case, the timer X interrupti request bit (bit 7 of inter-
rupt request register 1 (address 003C16)) is set to “1”.
When Timer X underflow
When input from INT0 pin is detected at the time of IGBT output
mode
Notes on Timer Y
1. Timer Y read/write control
When reading from/writing to timer Y, read from/write to both the
high-order and low-order bytes of timer Y. When the value is read,
read the high-order bytes first and the low-order bytes next. When
the value is written, write the low-order bytes first and the high-
order bytes next.
If reading from the timer Y register during write operation or writing
to it during read operation is performed, normal operation will not
be performed.
When writing a value to the timer Y address to write to the latch
only, the value is set into the reload latch and the timer is updated at
the next underflow. Normally, when writing a value to the timer Y
address, the value is set into the timer and the timer latch at the
same time, because they are set to write at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this time,
counting is stopped during writing to the high-order reload latch.
Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
2. CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of CNTR1
active edge switch bit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38C24M4-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38C24M4-XXXHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38C24M6-051HP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38C24M6-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38C24M6-XXXHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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