參數(shù)資料
型號(hào)： M38C24M4A-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 98/102頁(yè)
文件大?。?/td> 1369K
代理商： M38C24M4A-XXXFP
Rev.2.00
May 28, 2004
page 95 of 100
38C2 Group (A Version)
Fig. 5 Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit may be set to “1”.
When selecting external interrupt active edge
INT0 interrupt edge selection bit
(bit 0 of interrupt edge selection register (address 003A16))
INT1 interrupt edge selection bit
(bit 1 of interrupt edge selection register (address 003A16))
INT2 interrupt edge selection bit
(bit 2 of interrupt edge selection register (address 003A16))
CNTR0 active edge switch bit
(bit 6 of timer X control register (address 0FF416))
CNTR1 active edge switch bit
(bit 6 of timer Y mode register (address 003016))
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Interrupt edge selection register (address 003A16)
3. Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt request
bit of an interrupt request register immediately after this bit is set to
“0”, take the following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an inter-
rupt request bit of an interrupt request register is cleared to “0”, the
value of the interrupt request bit before being cleared to “0” is read.
Set the corresponding interrupt enable bit to “0” (disabled) .
↓
Set the interrupt edge select bit, active edge switch bit, or the
interrupt source select bit.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1” (enabled).
Set the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Fig. 6 Sequence of check of interrupt request bit
Notes on Interrupts
1. Unused interrupts
Set the interrupt enable bit for unused interrupts to “0” (disabled).
2. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous with
the following case, take the sequence shown in Figure 5.
When selecting external interrupt active edge
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Notes on Timer
1. When n (0 to 255) is written to a timer latch, the frequency divisin
ratio is 1/(n+1).
2. The timers share the one frequency divider to generate the count
source. Accordingly, when each timer starts operating, initializing
the frequency divider is not executed. Therefore, when the frequency
divider is selected for the count source, the delay of the maximum
one cycle of the count source is generated until the timer starts
counting or the waveform is output from timer starts operating. Also,
the count source cannot be checked externally.
3. Set the timer which is not used as follows:
Stop the count (when using a timer with stop control)
Set “0” to the corresponding interrupt enable bit
Notes on Timer X
1. CNTR0 active edge selection
The CNTR0 active edge selection bit (bit 6 of timer X mode register)
also effects the active edge of the generation of the CNTR0 inter-
rupt request.
When the pulse width is measured, set the bit 7 of the CNTR0 ac-
tive edge switch bits to “0”.
2. Write order to timer X
In the timer mode, pulse output mode, event counter mode and
pulse width measurement mode, write to the following registers in
the order as shown below;
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
Do not write to only one of them.
When the above mode is set and timer X operates as the 16-bit
counter, if the timer X register (extension) is never set after reset is
released, setting the timer X register (extension) is not required. In
this case, write the timer X register (low-order) first and the timer X
register (high-order). However, once writing to the timer X register
(extension) is executed, note that the value is retained to the reload
latch.
In the IGBT output and PWM modes, do not write “1” to the timer X
register (extension). Also, when “1” is already written to the timer X
register, be sure to write “0” to the register before using.
Write to the following registers in the order as shown below;
the compare register (high- and low-order),
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
It is possible to use whichever order to write to the compare regis-
ter (high- and low-order). However, write both the compare register
and the timer X register at the same time.
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