參數(shù)資料
型號(hào)： M38C24M4A-XXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 65/102頁(yè)
文件大?。?/td> 1369K
代理商： M38C24M4A-XXXFP
Rev.2.00
May 28, 2004
page 65 of 100
38C2 Group (A Version)
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read out
or rewritten easily, this MCU incorporates a ROM code protect func-
tion for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.
qROM Code Protect Function
The ROM code protect function is the function to inhibit reading out
or modifying the contents of internal flash memory by using the ROM
code protect control address (address FFDB16) in parallel I/O mode.
Figure 67 shows the ROM code protect control address (address
FFDB16). (This address exists in the User ROM area.)
If one or both of the pair of ROM code protect bits is set to “0”, the
ROM code protect is turned on, so that the contents of internal flash
memory are protected against readout and modification. The ROM
code protect is implemented in two levels. If level 2 is selected, the
flash memory is protected even against readout by a shipment in-
spection LSI tester, etc. When an attempt is made to select both
level 1 and level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal flash
memory can be readout or modified. Once the ROM code protect is
turned on, the contents of the ROM code protect reset bits cannot be
modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode
to rewrite the contents of the ROM code protect reset bits.
Fig. 67 Structure of ROM code protect control address
ROM code protect control address (address FFDB16)
ROMCP (FF16 when shipped)
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 3)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 1)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
b0
b7
Notes 1: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite
mode.
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