參數(shù)資料
型號: M38C24M4A-XXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 79/102頁
文件大?。?/td> 1369K
代理商: M38C24M4A-XXXFP
Rev.2.00
May 28, 2004
page 78 of 100
38C2 Group (A Version)
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(XCIN)
twH(XCIN)
twL(XCIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub clock input cycle time
Sub clock input “H” pulse width
Sub clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O1, 2 clock input cycle time (Note)
Serial I/O1, 2 clock input “H” pulse width (Note)
Serial I/O1, 2 clock input “L” pulse width (Note)
Serial I/O1, 2 input setup time
Serial I/O1, 2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(XCIN)
twH(XCIN)
twL(XCIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Limits
s
ns
s
ns
Parameter
Min.
2
100
1000(4 Vcc - 8)
40
45
40
45
20
9
200
1000(2 Vcc - 4)
85
105
85
105
80
800
370
220
100
Typ.
Max.
1000
500
Symbol
Unit
Limits
s
ns
s
ns
Parameter
Min.
2
125
50
20
9
750/(VCC–1)
tc(CNTR)/2–20
230
2000
950
400
200
Typ.
Max.
1000
500
Symbol
Unit
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub clock input cycle time
Sub clock input “H” pulse width
Sub clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O1, 2 clock input cycle time (Note)
Serial I/O1, 2 clock input “H” pulse width (Note)
Serial I/O1, 2 clock input “L” pulse width (Note)
Serial I/O1, 2 input setup time
Serial I/O1, 2 input hold time
Table 25 Timing requirements 2 (Flash memory version)
(Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Timing Requirements And Switching Characteristics
Table 24 Timing requirements 1 (Flash memory version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Note : When bit 6 of address 0FE016 or 0FE316 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 0FE016 or 0FE316 is “0” (UART).
Note : When bit 6 of address 0FE016 or 0FE316 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 0FE016 or 0FE316 is “0” (UART).
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
(4.5 V
≤ VCC ≤ 5.5 V)
(4.0 V
≤ VCC < 4.5 V)
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