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參數(shù)資料
| 型號： | M37920FCCGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī)) |
| 中文描述： | 單片微機(jī)16位的CMOS（16位單片機(jī)） |
| 文件頁數(shù)： | 61/158頁 |
| 文件大?。?/td> | 1261K |
| 代理商： | M37920FCCGP |
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61
M37920FCCGP, M37920FCCHP
M37920FGCGP, M37920FGCHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
MITSUBISHI MICROCOMPUTERS
Transmission
clock
TE
j
1/f
i
×
(n
+
1)
×
2
1/f
i
×
(n
+
1)
×
2
TI
j
CTS
j
Write in transmit buffer register
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
Transmit register
←
Transmit buffer register
Stopped because TE
j
=
“
0
”
CLK
j
T
ENDj
T
X
D
j
T
X
EPTY
j
Fig. 57 Clock synchronous serial I/O timing
Interrupt request at completion of reception
When the RIk flag changes from
“
0
”
to
“
1
”
, in other words, when the
receive operation is completed, the interrupt request bit of the
UARTk receive interrupt control register can be set to
“
1
”
.
The timing when this interrupt request bit is to be set to
“
1
”
can be
selected from the following:
Each reception
When an error occurs at reception
If bit 5 of the UARTk transmit/receive control register 0 (UARTk re-
ceive interrupt mode select bit) is cleared to
“
0
”
, the interrupt request
bit is set to
“
1
”
at each reception. If bit 5 is set to
“
1
”
, the interrupt re-
quest bit is set to
“
1
”
only when an error occurs. (In the clock syn-
chronous serial communication, only when an overrun error occurs,
the interrupt request bit is set to
“
1
”
.)
Note that a DMA request is affected by the UART receive interrupt
mode select bit if the UARTi reception is selected as a DMA request
source of the DMA controller.
When the UARTk receive interrupt mode select bit is cleared to
“
0
”
,
a DMA request is generated at each UART reception. When the
UARTk receive interrupt mode select bit is set to
“
1
”
, a DMA request
is generated only at normal UART reception. (In other words, no
DMA request is generated when an error has occurred.)
Polarity of transfer clock
In the clock synchronous serial communication, by bit 6 of the UARTj
transmit/receive control register 0 (CPL), the polarity of a transfer
clock can be selected.
As shown in Figure 58, when bit 6 =
“
0
”
, the polarity is as follows:
In transmission, transmit data is output at the falling edge of CLKj.
In reception, receive data is input at the rising edge of CLKk.
When not in transfer, CLKi is at
“
H
”
level.
When bit 6 =
“
1
”
, the polarity is as follows:
In transmission, transmit data is output at the rising edge of CLKj.
In reception, receive data is input at the rising edge of CLKk.
When not in transfer, CLKi is at
“
L
”
level.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37920FCCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920FGCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37920S4CGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16 BIT CMOS MICROCOMPUTER |
| M37P75C4P3 | 功能描述:汽車連接器 Pin Contact RoHS:否 制造商:Amphenol SINE Systems 產(chǎn)品:Contacts 系列:ATP 位置數(shù)量: 型式:Female 安裝風(fēng)格: 端接類型: 觸點電鍍:Nickel |
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