參數(shù)資料
型號： M37920FCCGP
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 16 Bits CMOS Microcomputer(16位單片機)
中文描述： 單片微機16位的CMOS（16位單片機）
文件頁數(shù)： 156/158頁
文件大?。?/td> 1261K
代理商： M37920FCCGP
Corrections and
Page
Supplement
ar
Erro
y
Explanation
r
for M37920FxC Dat
asheet (REV.
Correction
A) NO.4
(4/6)
Page 92,
Left column,
Lines 28, 29
Bi
t
2 of
select bit.
when it is “1”
page access is selected, t
page access mode
whi
ch
can
be speci
continuousl
y
during the f
ast page access,
be output
ag
ain aft
Then
,
the f
ast page access wil
Fi
gur
e 93 shows an operating waveform
DR
AM
control signal
access.
Bi
t
4 of
the DR
AM
sel
ect
the DR
Whe
ed.
AM
n
bi
, f
a
con
t
2 is “0”
page access is selected. When t
h
e
access suppo
o
f
DR
AM
i
s
perfor
f
i
ed with t
he same r
ccessed.
If
the row address
the new
er t
ha
t
fast
pag
l r
estart
t
rol register
, nor
is the access m
mal access is selected,
ode
st
he fast
ast
r
ting the f
the range
ad
dr
ess is
cha
nges
row addresses will
acce
ss
i
s
term
.
example of
ess bus in the f
med, if
ow
a
e
i
nat
ed
.
the
s
and
add
r
ast page
Bi
t
4 of
sel
ect
the DR
ed.
AM
DR
AM
control r
eg
ister
0
1
0
Access mode select bit
0: Nor
mal access
1: Fast
pa
ge
a
ccess
2
Page 95,
Fig. 90
DR
AM
control r
eg
ister
0
1
0
Fi
x
this bit to
“0”.
2
0
Operating waveform example of DRAM control signals
and address bus in fast page access
G
P
,
M37920F
8CHP
internal flash m
emory
(Deleted)
Page 117,
Right column,
Lines 15 to 17
area if
Note that,
the user
when the boot ROM
use
s
the flash m
emory
area
se
read
r
ial
I/O
mode.
i
s
area if the user uses the flash memory serial I/O mode.
Addresses FFB0
16
to FFBF
16
are the reserved area for
the serial programmer. Therefore, when the user uses
the flash memory serial I/O mode, do not program to this
area.
Note that, when the boot ROM area is read
M37920F8C
: block configuration of
(Deleted)
Page 118
RESET;
[Function]
The reset
i
nput
pi
n.
Input “
H
”
aft
e
r
“
L
”
is input.
The reset input pin.
P4
2
;
[Function]
This is an I/O pin for serial data.
This is an I/O pin for serial data. Connect this pin to V
CC
via a resistor (about 1 k
).
Thi
V
C
s
C
via a resistor
i
s
an
i
nput
pi
n
(about
for a
serial
1 k
)
cl
.
ock.
Co
nnect
this pin to
This is an input pin for a serial clock.
P4
4
;
[Function]
NMI;
[Function]
Input
“H”.
Input “H”, or leave this pin open.
Page 122,
Boot mode
progr
am the
u
ser
ROM
area.
program the user ROM area.
After reset removal, be sure not to change the status at
pins MD0 and MD1.
(Li
nes
22, 23)
(Li
nes
22, 23)
Page 122,
Fig. 120,
Note 4
4:
V
then clear
alid onl
y
w
to “0”
hen bit
1
= “
1”. Set
b
it
3 to “
1” (
reset)
, and
.
4:
Valid only when bit 1 = “1”. Set bit 3 to “1” (reset), and
then clear to “0”. This bit 3 must be controlled with the
CPU reprogramming mode select bit (bit 1) = “1”.
Page 99,
Right column,
Lines 1 to 3
When the wavefor
= bit
0 = “
become pulse output
When the wavefor
m output
P1
3
to
po
m output
sel
ect
RT
bits are
P0
3
, and RTP
set to
“11” (
0
2
bit 1
1”),
RT
R
r
TP1
0
,
t pins.
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), pulse output port pins are divided into two
groups; one consists of RTP1
3
to RTP1
0
, RTP0
3
, RTP0
2
and the other consists of RTP0
1
and RTP0
0
.
When the waveform output
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