
Corrections and
Page
Page 123,
Left column,
Lines 15 to 19
Supplement
ar
Erro
y
Explanation
r
for M37920FxC Dat
asheet (REV.
Correction
A) NO.5
(5/6)
Page 123,
Right column,
After line 24
request
occu
r
rence.
request
be sure
occu
no
r
rence.
to use
In the CPU
the
ST
reprogr
amming m
uction
od
e,
t
P
and
WIT
instr
s.
Page 124,
Fig. 121
The CP
(Wr
iting
U r
of “
e
pr
0”
→
Writing of
ogramm
i
ng
mode select bit is set
“1”)
to “
1”.
Writing of
bit.
(Wr
iting
“1”
to t
h
e
C
PU repr
og
r
amm
i
ng m
ode sele
ct
of “
0”
→
Writing of
“1”)
Page 124,
Software
Commands
(D
8
–D
1
5
)
is ignored.
(Li
nes
6, 7)
the 2nd cycle of
(D
8
–D
1
5
)
is ignored. (
a page progr
E
xcept
a
m
for
the write data
ming comm
at
and.)
(Li
nes
6, 7)
Page 125,
Page program
Command
, the same way as bit 7 of the status register.
Reading out the
(Lines 4 to 7)
, the same wayas bit 7 of the status register.
Before execution of the next command, be sure to verify
that bit 7 of the status register (SR.7) or the RY/BY
status bit is set to “1” (READY). During the automatic
programming operation, writing of commands and
access to the flash memory must not be performed.
Reading out the
nes
20 to
2
3)
, the same way as bit 7 of the status register.
Before execution of the next command, be sure to verify
that bit 7 of the status register (SR.7) or the RY/BY
status bit is set to “1” (READY). During the automatic
erase operation, writing of commands and access to the
flash memory must not be performed.
Reading out the
Page 125,
Block Erase
Command
(Li
, the same way as bit 7 of the status register.
Reading out the
nes
20 to
2
3)
(Li
Page 127,
E
r
ase Al
Unlocked
Co
l
B
mand
lock
m
(Lines 9 to 11)
is also reported by a read of the status register.
When the lock bit
(Lines 9 to 11)
is also reported by a read of the status register.
During the automatic erase execution (when the RY/BY
status bit = “0” ), writing of commands and access to the
flash memory must not be performed.
When the lock bit
er li
ne 20)
lock bit is ter
minated.
To perfor
m er
ase or pr
ogramm
the f
ol
lowi
ng.
By executing the r
ead lock bi
that
the lock of t
he target
bl
Set t
he lo
ck
bi
t
inva
lidity select bit t
the lock.
When the block er
ogramm
the lock
va
lid, t
he erase stat
ming st
a
t
us bit (SR.4)
are set
(Lines 4 to 7)
Page 124,
Page program
Command
(After line 20)
mode is m
ai
nt
a
ined.
(After line 20)
mode is m
if t
h
er
e is no progr
comm
ands can be executed with the r
mode kept
.
ai
nt
amming er
a
ined. I
n continuou
ror,
page program
s
program
ming,
ming
regi
ead status
st
er
Therefore,
must
be written only t
data writt
en to an odd addr
The write stat
e
a soft
w
ar
e comm
o an even address;
ess wi
a
nd
co
nsists
of 8-bit
therefor
id.
un
e, any
its
ll be inval
Therefore,
be writt
written
data at
sts
o
f
addresses.
The write stat
a soft
n
to an even address;
to an odd address will
the 2nd cycle of
16 bits,
thi
s
w
ar
e comm
a
nd
theref
be in
program
be written
co
nsisting of
o
r
e, any com
valid. Since
ming comm
to even and odd
8 bits must
mand
the write
an
d
con
e
a
si-
data must
e
Page 127,
D
ata
P
F
unction
(Blo
ck
r
otect
Lock)
(Aft
lock bit is ter
er li
ne 20)
minated.
(Aft
i
ng,
be sure t
o do one of
t
status
ock
i
s
command,
nvalid.
o “1”
to invali
verify
i
date
i
ng
i
s
p
an
i
nated by
er
form
d
program
ed wi
t
-
h
us bit (SR.5)
to “
1
”
(
term
error
).
(Titll
Pag
e)
e
P
r
og
r
am Com
mand (41
16
)
(Titlle)
Page Programming Command (41
16
)