參數(shù)資料
型號： M37902FGCHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 86/143頁
文件大?。?/td> 1148K
代理商： M37902FGCHP
47
M37902FCCHP, M37902FGCHP, M37902FJCHP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 35 Bit configuration of interrupt control register
76543210
Interrupt priority level select bits (Note 1)
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
76543210
Interrupt priority level select bits (Notes 1, 2)
Interrupt request bit
0 : No interrupt requested
1 : Interrupt requested
Polarity select bit
0 : Interrupt request bit is set to “1” at “H” level when level sense is selected;
this bit is set to “1” at falling edge when edge sense is selected.
1 : Interrupt request bit is set to “1” at “L” level when level sense is selected;
this bit is set to “1” at rising edge when edge sense is selected.
Level/Edge select bit
0 : Edge sense
1 : Level sense
Interrupt control register bit configuration for A-D converter, UART0, UART1,
timer A0 to timer A4, and timer B0 to timer B2.
Interrupt control register bit configuration for INT0– INT2
76543210
Interrupt priority level select bits
Interrupt request bit (Note 1)
0 : No interrupt requested
1 : Interrupt requested
Polarity select bit
0 : Interrupt request bit is set to “1” at falling edge.
1 : Interrupt request bit is set to “1” at rising edge.
Interrupt control register bit configuration for INT3 and INT4
Notes 1: Use the MOVM (MOVMB) instruction or the STA (STAB, STAD) instruction for writing to this bit.
2: Interrupt request bits of INT0 to INT2 are invalid when the level sense is selected.
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參數(shù)描述
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