參數(shù)資料
型號： M37902FGCHP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 79/143頁
文件大?。?/td> 1148K
代理商： M37902FGCHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
40
Fig. 28 Bit configuration of CS0/CS1/CS2/CS3 control register Ls
7
6
543
2
1
0
CS0 control register L
External data bus width select bit (Note 1)
0 : 16-bit width
1 : 8-bit width
RDY control bit (Note 2)
0 : RDY control is valid.
1 : RDY control is invalid.
Area CS0 bus cycle select bit 0
See Figure 18.
Address
8016
At reset
4216
Burst ROM access select bit (Note 3)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
0 : No recovery cycle is inserted at access to area CS0.
1 : Recovery cycle is inserted at access to area CS0.
CS0 output select bit (Notes 4, 5)
0 : CS0 output is disabled. (P44 functions as a programmble I/O port pin.)
1 : CS0 output is enabled. (P44 functions as pin CS0.)
Notes 1: While VSS level voltage is applied to pin BYTE, this bit’s state is cleared to “0” at reset. While VCC level voltage is
applied to pin BYTE, on the other hand, this bit’s state is set to “1” at reset.
2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”.
3: While VCC level voltage is applied to pin BYTE, the normal access is selected regardless of this bit’s contents.
4: In the single-chip mode, this bit’s contents are invalid. (CS0 output is disabled.)
5: While VSS level voltage is applied to pin MD0, this bit’s state is cleared to “0” at reset. While VCC level voltage is
applied to pin MD0, on the other hand, this bit’s state is set to “1” at reset. (Fixed to “1”.)
7
6
543
2
1
0
CS1 control register L
CS2 control register L
CS3 control register L
External data bus width select bit
0 : 16-bit width
1 : 8-bit width (Note 1)
RDY control bit (Note 2)
0 : RDY control is valid.
1 : RDY control is invalid.
Area CSj bus cycle select bit 0 (j = 1 to 3)
See Figure 18.
“0” at reading.
Address
8216
8416
8616
At reset
4216
Burst ROM access select bit (Note 3)
0 : Normal access
1 : Burst ROM access
Recovery cycle insert select bit
0 : No recovery cycle is inserted at access to area CSj.
1 : Recovery cycle is inserted at access to area CSj.
CSj output select bit (j = 1 to 3) (Note 4)
0 : CSj output is disabled. (P45 to P47 function as programmable I/O port pins.)
1 : CSj output is enabled. (P45 to P47 function as pin CSj.)
Notes 1: While VCC level voltage is applied to pin BYTE, this bit is fixed to “1” (8-bit width).
2: This bit is valid when the RDY input select bit (bit 2 at address 5F16) = “1”.
3: When only the external data bus width select bit (bit 2) = “1” or while VCC level voltage is applied to pin BYTE, the
normal access is selected regardless of this bit’s contents.
4: In the single-chip mode, this bit’s contents are invalid. (CS0 output is disabled.)
“0” at read.
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