參數(shù)資料
型號: M37902FGCHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 141/143頁
文件大?。?/td> 1148K
代理商: M37902FGCHP
97
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
WIT mode
When the WIT instruction is executed with the system clock stop se-
lect bit at WIT (bit 3 of the particular function select register 1 in Fig-
ure 101) being “0”,
φBIU, φCPU, and divide clocks Wf32 and Wf512 are
stopped in the “L“ state. However, the oscillation circuit, PLL circuit,
input clock fXIN, system clock fsys,
φ1, and peripheral devices’ clock
f1 to f4096 remain operating. Therefore, BIU and CPU are stopped,
whereas timers A and B, serial I/O, and the A-D converter, which use
the peripheral devices’ clocks f1 to f4096, are still operating. Note that
the watchdog timer is stopped.
On the other hand, when the WIT instruction is executed with the
system clock stop select bit at WIT being “1”, the oscillation circuit,
PLL circuit, and input clock fXIN are operating, while system clock
fsys,
φBIU, φCPU, and peripheral devices’ clocks stop operating. As a
result, the A-D converter and watchdog timer, which use peripheral
devices’ clocks f1 to f4096, Wf32 and Wf512, are stopped. At this time,
timers A and B operate only in the event counter mode, and serial
I/O communication is active only while an external clock is selected.
If the internal peripheral devices are not used in the WIT mode, the
latter is better because the current dissipation is more saved. Note
that the system clock stop select bit at WIT is to be set to “1” immedi-
ately before execution of the WIT instruction and cleared to “0” im-
mediately after the WIT mode is terminated.
The WIT state is terminated by acceptance of an interrupt request,
and then, supply of
φBIU and φCPU will restart. Since the oscillation
circuit, PLL circuit, and clock input fXIN are operating in the WIT
mode, an interrupt processing can be executed just after the WIT
mode termination.
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