參數(shù)資料
型號(hào): M37902FGCHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 68/143頁(yè)
文件大小: 1148K
代理商: M37902FGCHP
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M37902FCCHP, M37902FGCHP, M37902FJCHP
MITSUBISHI MICROCOMPUTERS
30
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
q Area multiplication
___
When area CS2’s external data bus width = 8 bits with the multi-
___
plexed bus select bit of the CS2 control register H (bit 5 at address
8516) = “1”, the external bus type can be changed to the multiplexed
___
bus type only at access to area CS2. In this case, the low-order 8 bits
of an address (LA0 to LA7) are output, and the low-order 8 bits of
data (D0 to D7) are input/output with the time-sharing method, re-
spectively.
Figure 22 shows a waveform example of area multiplication for each
bus cycle. Do not select the area multiplication function for a bus
cycle not shown in Figure 22.
Fig. 22 Waveform example of area multiplication for each bus cycle
D0 to D7
1 1
1 0
1 1
Multiplexed bus select bit = 1
Bus cycle
select bit 0
RD,
BLW
1 bus cycle = 6
φ
φ1
CSi
ALE
3
φ
3
φ
RD,
BLW
1 bus cycle = 7
φ
φ1
CSi
ALE
4
φ
3
φ
D0 to D7
External address bus
Address
External address bus
Address
Bus cycle 2
φ + 2φ
Bus cycle 3
φ + 3φ
Bus cycle 3
φ + 4φ
RD,
BLW
φ1
At write, LA0/D0 to LA7/D7
CSi
ALE
D0 to D7
1 bus cycle = 4
φ
D0 to D7
External address bus
Address
0
1
Area CS2 bus
cycle select
bit 0
At read, LA0/D0 to LA7/D7
At write, LA0/D0 to LA7/D7
At read, LA0/D0 to LA7/D7
At write, LA0/D0 to LA7/D7
At read, LA0/D0 to LA7/D7
LA0 to LA7
LA0 to LA7
Notes 1: The number of bus cycles is determined by the following bits:
Area CS2 bus cycle select bit 0 (bits 0 and 1 at address 8416)
Area CS2 bus cycle select bit 1 (bit 3 at address 8516)
Area multiplication is specified by the multiplexed bus select bit (bit 5 at address 8516).
2: Do not select the area multiplication function for a bus cycle not shown in Figure 22.
2
φ
2
φ
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