參數(shù)資料
型號(hào): M37902FGCHP
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, FLASH, 26 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 129/143頁(yè)
文件大?。?/td> 1148K
代理商: M37902FGCHP
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M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
86
INPUT/OUTPUT PINS
Ports P0 to P8, P10, P11 all have the direction register, and each bit
can be programmed for input or output. A pin becomes an output pin
when the corresponding bit of direction register is “1”, and an input
pin when it is “0”.
When a pin is programmed for output, the data is written to its port
latch and it is output to the output pin. When a pin is programmed for
output, the contents of the port latch is read instead of the value of
the pin. Accordingly, a previously output value can be read correctly
even when the output “H” voltage is lowered or the output “L” voltage
is raised owing to an external load, etc.
A pin programmed as an input pin is in the flooting state, and the
value input to the pin can be read. When a pin is programmed as an
input pin, the data is written only in the port latch and the pin remains
floating.
Each of Figures 89 and 90 shows the block diagram for each port pin
and pin NMI. Figure 91 shows the bit configuration of the port func-
tion control register.
Bit 3 of the port function control register serves as the port P0 input
level select bit, which selects the VIH/VIL level under the condition
that port P0 is used as an input port.
Bit 4 of the port function control register serves as the P44–P47
pullup connection select bit. This bit determines whether port pins
P44–P47, which are multiplexed with chip select pins, are to be
pulled up or not. At reset, this bit 4 = “0” and P4–P47 are pulled up.
The pullup function is valid only when the corresponding port is used
an input port.
Bit 7 of the port function control register serves as the NMI pullup
connection select bit. At reset, this bit 7 = “0” and pin NMI is pulled
up. The pullup function is valid only when the corresponding port is
used as an input port.
When using port pins P54–P57 as the key input interrupt input pins
(KI0 to KI3), the pullup function can be selected, also. For details,
refer to the section on interrupts.
When using a port pin as an internal peripheral device’s input pin,
clear the corresponding port direction register’s bit to “0”. When us-
ing a port pin as an internal peripheral device’s output pin, the port
direction register’s bit may be “0” or “1”.
In the memory expansion or microprocessor mode, port pins of P0 to
P4, P10, P11 become I/O pins, and the their functions as I/O port
pins are invalid. Note that, however, some port pins can function as
port pins by the special setting. For details, refer to the section on the
processor modes.
Fig. 91 Bit configuration of port function control register
Notes 1: For the M37902FxM (power source voltage = 3.3 V
±0.3 V), VIH = 0.5VCC.
2: When MD1 = VCC and MD0 = VCC (flash memory parallel I/O mode), pins P44 to P47 and NMI are
not pulled up, regardless of these bits’ contents.
3: When MD1 = VSS and MD0 = VCC (microprocessor mode), pin CS0 (P44) is not pulled up, regardless of the bit’s contents.
7
6
543
2
1
0
Port function control register
Port P0 input level select bit
0 : VIH = 0.7VCC, VIL = 0.2VCC
1 : VIH = 0.43VCC (Note 1), VIL = 0.16VCC
Address/Port switch bits
000 : A0 to A23 (16 Mbytes)
001 : A0 to A21, P06, P07 (4 Mbytes)
010 : A0 to A19, P04 to P07 (1 Mbytes)
011 : A0 to A17, P02 to P07 (256 Kbytes)
100 : A0 to A15, P00 to P07 (64 Kbytes)
101 : Do not select.
110 : A0 to A11, P00 to P07, P114 to P117 (4 Kbytes)
111 : A0 to A7, P00 to P07, P110 to P117 (256 bytes)
Pins P44–P47 pullup connection select bit (Notes 2 and 3)
0 : Pins P44–P47 are pulled up.
1 : Pins P44–P47 are not pulled up.
Address
9216
Pin NMI pullup connection select bit (Note 2)
0 : Pin NMI is pulled up.
1 : Pin NMI is not pulled up.
Fix these bits to “0”.
0
At reset
0016
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