參數(shù)資料
型號: M37641F8FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件頁數(shù): 97/140頁
文件大?。?/td> 1694K
代理商: M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 4 of 135
REJ03B0191-0400
P50/XCIN,
P51/TOUT/
XCOUT,
P52/OBF0,
P53/IBF0,
P54/S0,
P55/A0,
P56/R(E),
P57/W(R/W)
Apply 4.15 V – 5.25 V for 5 V version or 3.00 V – 3.60 V for 3 V version to the Vcc pin. Apply 0 V to the
Vss pin.
This controls the MCU operating mode. Connect this pin to Vss. If connecting this pin to Vcc, the
internal ROM is inhibited. In the flash memory version this pin functions as a VPP power supply input pin.
These pins are the power supply inputs for analog circuitry.
Reset input pin for active “L.”
Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
Loop filter for the frequency synthesizer.
It is a capacitor connection pin for built-in DC-DC converter. At Vcc=5 V, use built-in DC-DC converter
by permitting a USB line driver and connect a capacitor. Refer to "Notes on use" for details. Built-in DC-
DC converter cannot be used at Vcc = 3.3 V. Supply 3.3V power supply to this pin from the externals.
USB D+ voltage signal port. Connect a 27 to 33
(recommended) resistor in series.
USB D- voltage signal port. Connect a 27 to 33
(recommended) resistor in series.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
When connecting an external memory, these function as the address bus.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
When connecting an external memory, these function as the address bus.
Key-on wake-up interrupt input pin
VCC, VSS
CNVss/VPP
AVss/AVcc
RESET
XIN
XOUT
LPF
Ext. Cap.
USB D+
USB D-
P00/AB0
P07/AB7
Name
Power source
CNVss
Analog power
supply
Reset input
Clock input
Clock output
LPF
3.3 V line power
supply
USB D+
USB D-
Function except a port function
PIN DESCRIPTION
Table 1 Pin description (1)
Function
P10/AB8
P17/AB15
P20/DB0
P27/DB7
8-bit I/O port.
CMOS compatible input level or VIHL input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
When connecting an external memory, these function as
the data bus.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
When connecting an external memory, these function as
the control bus.
P30/RDY,
P31, P32,
P33/DMAOUT,
P34/
φ OUT,
P35/SYNCOUT,
P36/WR,
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
When connecting an external memory, these function as
the control bus.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
When enabling the Master CPU bus interface function,
CMOS or TTL input level can be selected as an input.
I/O port P0
I/O port P1
I/O port P2
I/O port P3
(See Remarks.)
External memory control pin
I/O port P4
P37/RD
P40/EDMA,
P41/INT0,
P42/INT1,
P43/CNTR0,
P44/CNTR1
External memory control pin
External interrupt pin
Timer X, Timer Y pin
Sub-clock generating input pin
Timers 1, 2 pulse output pins
Sub-clock generating output pin
Master CPU bus interface pin
Pin
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