參數(shù)資料
型號(hào): M37641F8FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件頁數(shù): 71/140頁
文件大?。?/td> 1694K
代理商: M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 34 of 135
REJ03B0191-0400
UTXD output (P84/UTXD1,
P80/UTXD2/SRDY)
D0
D1
SP
ST
D2
D3
D4
D5
D6
D7
P
SP
Transfer clock
Tranmit enable bit
Transmit buffer
empty flag
Transmit complete flag
D0
D1
D2
D3
D4
D5
D6
D7
ST
P
D0
D1
ST
Data set into UARTx transmit buffer register 1
Data transferring from UARTx transmit
buffer register 1 to Transmit shift register 1
This timing applies to the conditions:
Character length = 8 bits
Parity enabled
1 stop bit
qRTS (Request-to-Send) Function
As a receiver, the UART can be configured to generate the Re-
quest-to-Send (RTSx) handshaking signal. This is enabled by
setting the RTS Function Enable Bit (bit 6 of UxCON) to “1”.
When reception is enabled, that is the Receive Enable Bit is “1”,
the RTSx pin goes “L” to inform a transmitter that reception is pos-
sible. The RTSx pin goes “H” at reception starting and does “L” at
receiving of the last bit.
The delay time from the reception of the last stop bit to the asser-
tion of RTSx is selectable using the RTS Assertion Delay Count
Select Bits.
BRGx (x = 1, 2)
count source
D0
URXD (P85/URXD1,
P81/URXD2/SCLK)
ST
SP
D1
D7
RTSx pin (P87/RTS1,
P83/RTS2/STXD)
Receive enable bit
Receive buffer
empty flag
Transfer clock
Transfer clock generated at falling edge
of start bit and receive started
Receive data latched
Data transferring from UARTx receive register
1 to Receive buffer register 1 (Note)
Note: When no RTS assertion delay, the RTSx pin goes “L”.
The RTS assertion delay counts are selected by bits 4 to 7 of UARTx RTS control register.
This timing applies to the conditions:
Character length = 8 bits
Parity enabled
1 stop bit
Fig. 28 UARTx transmit timing (CTS function disbled)
When the Receive Enable Bit is set to “0” or the Receive initializa-
tion bit is set to “1”, the RTSx pin goes “H”. Even when the
Receive Enable Bit is set to “1”, the RTSx pin goes “H” if detecting
an invalid start bit.
Figure 29 shows the UARTx receive timing.
Fig. 29 UARTx transmit timing (RTS function enabled)
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