參數(shù)資料
型號: M37641F8FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件頁數(shù): 44/140頁
文件大?。?/td> 1694K
代理商: M37641F8FP
REVISION HISTORY
7641 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
(1/ )
1.0
04/06/2001
First edition
Page 1
Page 104
Page 105
Page 145
Page 146
2.0
05/17/2001
Notes 2 are added.
Fig.89 is revised: Explanation of bits 5 to 7 and Notes.
Fig.90 is revised: Explanation of flow chart.
“USB Transceiver Treatment” Line 9 is revised: “between the USB D+ pin and
USB D- pin, or” is deleted.
URL of Mitsubishi MCU Technical Information Homepage is revised:
http://www.infomicom.maec.co.jp
3.0
12/27/2001 Page 1
Page 4
Page 6
Page 11
Page 22
Page 31
Page 38
Page 39
Page 42
Page 44
Page 45
Page 46
Page 53
Page 55
Page 75
Page 80
Page 88
Page 91
Page 94
Pages 102
to 128
Page 130
Page 131
Page 132
Operating temperature range is added.
Table 1 is revised: Ext. Cap. function’s explanation is revised.
Fig.4 is revised: “A-” is eliminated.
Fig.8 is revised: Bit 4 explanation of CPMA is revised.
Fig.17 is revised: The symbol of Interrupt control register C is corrected.
The pin name SRD is corrected to SRDY.
Fig.31 is revised: Serial I/O as interrupt is eliminated.
Fig.32 is revised: Bit 5 explanation of DMAxM1 is revised.
The flag name in section Priority is corrected to the DMAC Channel x (x =0, 1)
Suspend Flag (DxSFI).
The explanation of section “Interrupt transfer mode” is revised.
Some explanations of section “USB Reception” is eliminated.
The all USB internal registers addresses in section USB Function Interrupt is cor-
rected to “005F16”.
The explanation of section “IN_CSR” is revised.
Fig.48 is revised: Bits 0 and 3 name of OUT_CSR is corrected.
Fig.70 is revised: Bit 4 explanation of CPMA is revised.
Table 10 is revised: AVcc and Ext. Cap. as a parameter is added.
Table 18 is revised: Ext. Cap. limits are added.
Table 20 is revised: Test conditions to be determined are eliminated.
Table 24 is revised: The parameter of td(WR-DB) is revised.
The explanation of section “FLASH MEMORY MODE” is revised.
The all USB internal registers addresses in section USB Function Interrupt is cor-
rected to “005F16”.
The explanation of IN_PKT_RDY is revised.
The explanation of section “DMA” is revised.
The explanation of section “USB Transceiver Treatment” is added: In Vcc = 5 V.
3.1
3/26/2002
Page 1
Page 7
Page 102
Page 115
Page 133
Power source voltage and Program/Erase voltage of Flash memory mode in FEA-
TURES are updated.
Fig. 5 is revised: “M37641F8” is in Mass-production status.
Table 25 is revised.
Table 28 is revised.
One usage note is added: Electric Characteristic Differences Between Mask ROM
and Flash Memory Version MCUs
4.0
8/28/2006 All pages
All pages
38
Package names “80P6N-A”
→ “PRQP0080GB-A” revised
Package names “80P6Q-A”
→ “PLQP0080KB-A” revised
“USB std. spec. ver.1.1”
→ “Full-Speed USB2.0 specification”
DMAC; “(DxCEN)”
→ “(DxHR)”
2
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