參數(shù)資料
型號： M37641F8FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件頁數(shù)： 57/140頁
文件大?。?/td> 1694K
代理商： M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 21 of 135
REJ03B0191-0400
Interrupt Source
Reset (Note 3)
USB function
USB SOF
INT0
INT1
DMAC0
DMAC1
UART1 receive
buffer full
UART1 transmit
UART1
summing error
UART2 receive
buffer full
UART2 transmit
UART2
summing error
Timer X
Timer Y
Timer 1
Timer 2
Timer 3
CNTR0
CNTR1
Serial I/O
Input buffer full
Output buffer
empty
Key input (Key-
on wake-up)
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Vector Addresses (Note 1)
High
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFDB16
FFD916
FFD716
FFD516
FFD316
FFD116
FFCF16
FFCD16
FFCB16
Interrupt Request
Generating Conditions
At reset
(Note 2)
At reception of SOF packet
At detection of either rising or falling edge of
INT0 intput
At detection of either rising or falling edge of
INT1 input
At completion of DMAC0 transfer
At completion of DMAC1 transfer
At completion of UART1 reception
At completion of UART1 transmission
At detection of UART1 summing error
At completion of UART2 reception
At completion of UART2 transmission
At detection of UART2 summing error
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At completion of serial I/O transmission/re-
ception
At writing to input data bus buffer
At reading from output data bus buffer
At falling of port P2 input logical level AND
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Low
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFDA16
FFD816
FFD616
FFD416
FFD216
FFD016
FFCE16
FFCC16
FFCA16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: USB function interrupt occurs owing to an interrupt request of the endpoint x (x = 0 to 4) IN, endpoint x OUT, overrun/underrun, USB reset or suspend/
resume.
3: Reset functions in the same way as an interrupt with the highest priority.
Table 7 Interrupt vector addresses and priority
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(falling valid)
Non-maskable software interrupt
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