參數(shù)資料
型號: M37641F8FP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件頁數(shù): 88/140頁
文件大?。?/td> 1694K
代理商: M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 49 of 135
REJ03B0191-0400
[USB Interrupt Status Registers 1 and 2] USBIS1, USBIS2
The USB interrupt status registers are used to indicate the condi-
tion that caused a USB function interrupt to be generated. Each
status flag and bit can be cleared to “0” by writing “1” to the corre-
sponding bit. Make sure to write to/read from the USB interrupt
status register 1 first and then USB interrupt status register 2.
When an IN token is received during an isochronous transfer, and
USB interrupt status register 1 (address 005216)
USBIS1
USB endpoint 0 interrupt status flag (INTST0)
0: Except the following conditions
1: Set at any one of the following conditions:
A packet data of endpoint 0 is successfully received
A packet data of endpoint 0 is successfully sent
DATA_END bit of endpoint 0 is cleared to “0”
FORCE_STALL bit of endpoint 0 is set to “1”
SETUP_END bit of endpoint 0 is set to “1”.
Reserved bit (“0” at read/write)
USB endpoint 1 IN interrupt status flag (INTST2)
0: Except the following conditions
1: Set at which of the following conditions:
A packet data of endpoint 1 is successfully sent
UNDER_RUN bit of endpoint 1 is set to “1”.
USB endpoint 1 OUT interrupt status flag (INTST3)
0: Except the following conditions
1: Set at any one of the following conditions:
A packet data of endpoint 1 is successfully received
OVER_RUN bit of endpoint 1 is set to “1”
FORCE_STALL bit of endpoint 1 is set to “1”.
USB endpoint 2 IN interrupt status flag (INTST4)
0: Except the following conditions
1: Set at which of the following conditions:
A packet data of endpoint 2 is successfully sent
UNDER_RUN bit of endpoint 2 is set to “1”.
USB endpoint 2 OUT interrupt status flag (INTST5)
0: Except the following conditions
1: Set at any one of the following conditions:
A packet data of endpoint 2 is successfully received
OVER_RUN bit of endpoint 2 is set to “1”
FORCE_STALL bit of endpoint 2 is set to “1”.
USB endpoint 3 IN interrupt status flag (INTST6)
0: Except the following conditions
1: Set at which of the following conditions:
A packet data of endpoint 3 is successfully sent
UNDER_RUN bit of endpoint 3 is set to “1”.
USB endpoint 3 OUT interrupt status flag (INTST7)
0: Except the following conditions
1: Set at any one of the following conditions:
A packet data of endpoint 3 is successfully received
OVER_RUN bit of endpoint 3 is set to “1”
FORCE_STALL bit of endpoint 3 is set to “1”.
b0
b7
0
the IN FIFO is empty, an underrun error occurs and INTST12 and
IN_CSR2 are set to “1”. When an OUT token is received and the
OUT FIFO is full, an overrun error occurs and INTST12 and
OUT_CSR2 are set to “1”. Underruns and overruns are not de-
tected by the CPU in bulk transfers and normal interrupt transfers,
however in this case, the MCU will send a NAK signal to the host
CPU.
Fig. 40 Structure of USB interrupt status register 1
相關(guān)PDF資料
PDF描述
M37641M8-XXXFP 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80
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M37643F8HP 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
M37643M8-XXXHP 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
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