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5
INTERRUPT CONTROLLER (ICU)
5-12
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
5.4 ICU Vector Table
The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The
40-source interrupt requests are assigned the following vector table addresses.
The interrupt request sources are also assigned the following hardware fixed priority levels.
Table 5.4.1 ICU Vector Table
Priority
Interrupt Request Source
ICU Vector Table Address
Number of
ICU Type of Input
Input Source
Source (Note 1)
High
MJT input interrupt 4
H'0000 0094
– H'0000 0097
4
Level-recognized
MJT input interrupt 3
H'0000 0098
– H'0000 009B
8
Level-recognized
MJT input interrupt 2
H'0000 009C – H'0000 009F
4
Level-recognized
MJT input interrupt 1
H'0000 00A0 – H'0000 00A3
1
Level-recognized
MJT input interrupt 0
H'0000 00A4 – H'0000 00A7
5
Level-recognized
MJT output interrupt 7
H'0000 00A8 – H'0000 00AB
2
Level-recognized
MJT output interrupt 6
H'0000 00AC – H'0000 00AF
2
Level-recognized
MJT output interrupt 5
H'0000 00B0 – H'0000 00B3
1
Edge-recognized
MJT output interrupt 4
H'0000 00B4 – H'0000 00B7
4
Level-recognized
MJT output interrupt 3
H'0000 00B8 – H'0000 00BB
2
Level-recognized
MJT output interrupt 2
H'0000 00BC – H'0000 00BF
6
Level-recognized
MJT output interrupt 1
H'0000 00C0 – H'0000 00C3
2
Level-recognized
MJT output interrupt 0
H'0000 00C4 – H'0000 00C7
4
Level-recognized
DMA0–4 interrupt
H'0000 00C8 – H'0000 00CB
5
Level-recognized
SIO1 receive interrupt
H'0000 00CC – H'0000 00CF
1
Edge-recognized
SIO1 transmit interrupt
H'0000 00D0 – H'0000 00D3
1
Edge-recognized
SIO0 receive interrupt
H'0000 00D4 – H'0000 00D7
1
Edge-recognized
SIO0 transmit interrupt
H'0000 00D8 – H'0000 00DB
1
Edge-recognized
A/D0 conversion interrupt
H'0000 00DC – H'0000 00DF
1
Edge-recognized
TID0 output interrupt
H'0000 00E0 – H'0000 00E3
1
Edge-recognized
TOU0 output interrupt
H'0000 00E4 – H'0000 00E7
8
Level-recognized
DMA5–9 interrupt
H'0000 00E8 – H'0000 00EB
5
Level-recognized
SIO2,3 transmit/receive interrupt
H'0000 00EC – H'0000 00EF
4
Level-recognized
RTD interrupt
H'0000 00F0
– H'0000 00F3
1
Edge-recognized
TID1 output interrupt
H'0000 00F4
– H'0000 00F7
1
Edge-recognized
TOU1 output interrupt
H'0000 00F8
– H'0000 00FB
8
Level-recognized
SIO4,5 transmit/receive interrupt
H'0000 00FC – H'0000 00FF
4
Level-recognized
TML1 input interrupt
H'0000 0108
– H'0000 010B
4
Level-recognized
CAN0 transmit/receive & error interrupt
H'0000 010C – H'0000 010F
67
Level-recognized
CAN1 transmit/receive & error interrupt
H'0000 0110
– H'0000 0113
67
Level-recognized
DRI transfer interrupt
H'0000 0114
– H'0000 0117
5
Level-recognized
DRI counter interrupt
H'0000 0118
– H'0000 011B
5
Level-recognized
DRI event detection interrupt
H'0000 011C – H'0000 011F
6
Level-recognized
CAN0 transmit/receive interrupt
H'0000 0120
– H'0000 0123
32
Level-recognized
CAN0 single-shot interrupt
H'0000 0124
– H'0000 0127
32
Level-recognized
CAN0 error interrupt
H'0000 0128
– H'0000 012B
3
Level-recognized
CAN1 transmit/receive interrupt
H'0000 012C – H'0000 012F
32
Level-recognized
CAN1single-shot interrupt
H'0000 0130
– H'0000 0133
32
Level-recognized
CAN1 error interrupt
H'0000 0134
– H'0000 0137
3
Level-recognized
Low
RAM write monitor interrupt
H'0000 0138
– H'0000 013B
16
Level-recognized
Note 1: ICU type of input source
Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.
Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For
this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.