
DIRECT RAM INTERFACE (DRI)
14
14-36
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
14.2.16 DRI Event Counters (DEC Counters)
DEC0 Counter (DEC0CT)
<Address: H'0080 2036>
DEC1 Counter (DEC1CT)
<Address: H'0080 203C>
DEC2 Counter (DEC2CT)
<Address: H'0080 2042>
DEC3 Counter (DEC3CT)
<Address: H'0080 2048>
DEC4 Counter (DEC4CT)
<Address: H'0080 204E>
b0
123456789
10
11
12
13
14
b15
DECnCT
0000000000000000
<Upon exiting reset: H'0000>
b
Bit Name
Function
R
W
0–15
DECnCT
RW
DECn counter
Note: This register must always be accessed in halfword (16 bits) units from the halfword boundaries.
The DECn Counter, which is a 16-bit down counter, starts counting synchronously with event detection after
count is enabled. When DECn counter is used in one-shot mode, do not write to the DECn counter while count
is enabled.
14.2.17 DRI Event Counter (DEC) Reload Registers
DEC0 Reload Register (DEC0RLD)
<Address: H'0080 2034>
DEC1 Reload Register (DEC1RLD)
<Address: H'0080 203A>
DEC2 Reload Register (DEC2RLD)
<Address: H'0080 2040>
DEC3 Reload Register (DEC3RLD)
<Address: H'0080 2046>
DEC4 Reload Register (DEC4RLD)
<Address: H'0080 204C>
b0
123456789
10
11
12
13
14
b15
DECnRL
0000000000000000
<Upon exiting reset: H'0000>
b
Bit Name
Function
R
W
0–15
DECnRL
RW
DECn reload value
Note: This register must always be accessed in halfword (16 bits) units from the halfword boundaries.
The DECn Reload Register is used to reload the DECn Counter with data. The counter is reloaded with the
content of the reload register in the following cases:
When count is enabled while being disabled in single-shot mode
When the DECn counter underflows while operating in continuous operation mode
14.2 DRI Related Registers