
A/D CONVERTER
11
11-41
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
11.3 Functional Description of A/D Converter
Table 11.3.4 Conversion Clock Periods for Simultaneous Sampling when Normal Sample-and-Hold is
Enabled (Shortest Period)
Unit: BCLK
Conversion speed
Start dummy
Execution
Channel to
Execution
End
(Note 1)
cycle 1
channel dummy
cycle 2
dummy
2BCLK mode
Slow mode
Normal speed
8
588
8
588
2
Double speed
8
336
8
336
2
Fast mode
Normal speed
8
252
8
252
2
Double speed
8
168
8
168
2
Note 1: The same applies to both software and hardware triggers.
Table 11.3.5 Conversion Clock Periods for Simultaneous Sampling when Fast Sample-and-Hold is Enabled
(Shortest Period)
Unit: BCLK
Conversion speed
Start dummy
Execution
Channel to
Execution
End
(Note 1)
cycle 1
channel dummy
cycle 2
dummy
2BCLK mode
Slow mode
Normal speed
8
372
8
372
2
Double speed
8
192
8
192
2
Fast mode
Normal speed
8
180
8
180
2
Double speed
8
96
8
96
2
Note 1: The same applies to both software and hardware triggers.
(4) Calculating the conversion time during simultaneous sampling conversion
The following schematically shows the method for calculating the conversion time during the simultaneous
sampling conversion.
Figure 11.3.6 Conceptual Diagram of A/D Conversion Time during Simultaneous Sampling Conversion
Start
dummy
End
dummy
Sampling
time
Sampling
dummy time
Channel to
channel dummy
Execution cycle 1
Start trigger
Convert operation
starts
Completed
Execution cycle 2