參數(shù)資料
型號(hào)： LPC2460
廠商： NXP Semiconductors N.V.
英文描述： Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface
中文描述： 毛邊16-bit/32-bit微，以太網(wǎng)，CAN，供應(yīng)商/國(guó)際檢察官聯(lián)合會(huì)，USB 2.0設(shè)備/主機(jī)/ OTG功能，外部存儲(chǔ)器接口
文件頁(yè)數(shù)： 33/67頁(yè)
文件大?。?/td> 340K
代理商： LPC2460
LPC2460_0
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 00.01 — 5 October 2007
33 of 67
NXP Semiconductors
LPC2460
Fast communication chip
Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
Full CAN messages can generate interrupts.
7.12 10-bit ADC
The LPC2460 contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.12.1
Features
10-bit successive approximation ADC
Input multiplexing among 8 pins
Power-down mode
Measurement range 0 V to V
i(VREF)
10-bit conversion time
≥
2.44
μ
s
Burst conversion mode for single or multiple inputs
Optional conversion on transition of input pin or Timer Match signal
Individual result registers for each ADC channel to reduce interrupt overhead
7.13 10-bit DAC
The DAC allows the LPC2460 to generate a variable analog output. The maximum output
value of the DAC is V
i(VREF)
.
7.13.1
Features
10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive
7.14 UARTs
The LPC2460 contains four UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface.
The UARTs include a fractional baud rate generator. Standard baud rates such as 115200
can be achieved with any crystal frequency above 2 MHz.
7.14.1
Features
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
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參數(shù)描述
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