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參數(shù)資料
| 型號(hào)： | LPC2460 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface |
| 中文描述： | 毛邊16-bit/32-bit微，以太網(wǎng)，CAN，供應(yīng)商/國際檢察官聯(lián)合會(huì)，USB 2.0設(shè)備/主機(jī)/ OTG功能，外部存儲(chǔ)器接口 |
| 文件頁數(shù)： | 28/67頁 |
| 文件大?。?/td> | 340K |
| 代理商： | LPC2460 |
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LPC2460_0
NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 00.01 — 5 October 2007
28 of 67
NXP Semiconductors
LPC2460
Fast communication chip
–
Asynchronous page mode read
–
Programmable Wait States
–
Bus turnaround delay
–
Output enable and write enable delays
–
Extended wait
Four chip selects for synchronous memory and four chip selects for static memory
devices.
Power-saving modes dynamically control CKE and CLKOUT to SDRAMs.
Dynamic memory self-refresh mode controlled by software.
Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is
typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device.
Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note:
Synchronous static memory devices (synchronous burst mode) are not supported.
7.7 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2460
peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
7.7.1
Features
Two DMA channels. Each channel can support a unidirectional transfer.
The GPDMA can transfer data between the 16 kB SRAM, external memory, and
peripherals such as the SD/MMC, two SSPs, and the I
2
S interface.
Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time, the channel with the
highest priority is serviced first.
AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
One AHB bus master for transferring data. This interface transfers data when a DMA
request goes active.
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| LPC2460_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Flashless 16-bit/32-bit micro; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface |
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| LPC2460FBD208-S | 制造商:NXP Semiconductors 功能描述:MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC ROMLess 3.3V 208-Pin LQFP Tray |
| LPC2460FET208 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Flashless 16-bit/32-bit microcontroller; Ethernet, CAN, ISP/IAP, USB 2.0 device/host/OTG, external memory interface |
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