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參數(shù)資料
| 型號： | LP3972 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Power Management Unit for Advanced Application Processors |
| 中文描述： | 電源管理單元的高級應(yīng)用處理器 |
| 文件頁數(shù)： | 6/59頁 |
| 文件大?。?/td> | 1072K |
| 代理商： | LP3972 |
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Pin Descriptions
Pin #
1
Name
PWR_ON
I/O
I
Type
D
Description
CPU Wakeup input, this can be a push button event to indicate the
device has been turned on. Phone / PDA main power button. Signal
is debounced internally on the PMIC.
If the POWER_ON is held low this will indicate to the PMIC to turn
off. Active high Polarity
This is a input signal used for a turn on event coming from the bed
of nails tester during production. Active low polarity.
CPU Wakeup input to indicate that a HW external event has
occurred, i.e. flipping the cell phone to power up the display.
This signal is asserted when DC POWER source has been
asserted, or when the PWR_ON button is held down to turn off the
PMIC. Wake up on power detection, and power down detection.
Buck1 input feedback terminal
Battery Input (Internal circuitry and LDO1-3 power input)
LDO1 output
LDO2 output
Active low Reset pin. Signal used to reset the IC (by default is
pulled high internally). Typically a push button reset.
Ground
Bypass Cap. for the high internal impedance reference.
LDO3 output
LDO4 output
Power input to LDO4, this can be connected to either from a 1.8V
supply to main Battery supply.
Back Up Battery input supply.
LDO_RTC output supply to the RTC of the application processor.
2
nTEST_JIG
I
D
3
SPARE
I
D
4
EXT_WAKEUP
O
D
5
6
7
8
9
FB1
V
IN
I
I
A
PWR
PWR
PWR
D
V
OUT
LDO1
V
OUT
LDO2
nRSTI
O
O
I
10
11
12
13
14
GND1
VREF
V
OUT
LDO3
V
OUT
LDO4
V
IN
LDO4
G
O
O
O
I
G
A
PWR
PWR
PWR
15
16
V
IN
BUBATT
V
OUT
LDO_RTC
nBATT_FLT
I
PWR
PWR
O
17
O
D
Main Battery fault output, indicates the main battery is low
(discharged) or the dc source has been removed from the system.
This gives the processor an indicator that the power will shut down.
During this time the processor will operate from the back up coin
cell.
Buck2 NMOS Power Ground
Buck2 switcher output
Battery input power to Buck2
I
2
C Data (Bidirectional)
I
2
C Clock
Buck2 input feedback terminal
Reset output from the PMIC to the processor
LDO5 output
Power input to LDO5, this can be connected to V
IN
or to a separate
1.8V supply.
Analog Power for VREF, BIAS
Buck3 Feedback
General Purpose I/O / Ext. backup battery charger enable pin. This
pin enables the main battery / DC source power to charge the
backup battery. This pin toggled via the application processor. By
grounding this pin the DC source continuously charges the backup
battery
General Purpose I/O
Battery input power to Buck3
18
19
20
21
22
23
24
25
26
PGND2
SW2
V
IN
Buck2
SDA
SCL
FB2
nRSTO
V
OUT
LDO5
V
IN
LDO5
G
O
I
I/O
I
I
O
O
I
G
PWR
PWR
D
D
A
D
PWR
PWR
27
28
29
VDDA
FB3
GPIO1 /
nCHG_EN
I
I
PWR
A
D
I/O
30
31
GPIO2
V
IN
Buck3
I/O
I
D
PWR
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP3972_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Power Management Unit for Advanced Application Processors |
| LP3972SQ-0514/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3972SQ-5810/NOPB | 功能描述:監(jiān)控電路 Pwr Mgmt Unit RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| LP3972SQ-A413 | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3972SQ-A413/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
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