參數(shù)資料
型號(hào): LP3972
廠商: National Semiconductor Corporation
英文描述: Power Management Unit for Advanced Application Processors
中文描述: 電源管理單元的高級(jí)應(yīng)用處理器
文件頁(yè)數(shù): 24/59頁(yè)
文件大?。?/td> 1072K
代理商: LP3972
I
2
C Compatible Interface
(Continued)
LP3972 CONTROL REGISTER
Register Address
8h’07
8h’10
8h’11
8h’12
8h’13
8h’20
8h’23
8h’24
8h’25
8h’26
8h’27
8h’29
8h’2A
8h’32
8h’33
8h’39
8h’3A
8h’80
8h’81
8h’82
8h’83
8h’84
8h’85
8h’86
8h’87
8h’88
8h’89
8h’8E
8h’8F
Register Name
SCR
OVER1
OVSR1
OVER2
OVSR2
V
CC
1
ADTV1
ADTV2
AVRC
CDTC1
CDTC2
SDTV1
SDTV2
MDTV1
MDTV2
L2VCR
L34VCR
SCR1
SCR2
OEN3
OSR3
LOER4
B2TV
B3TV
B32RC
ISRA
BCCR
II1RR
II2RR
Read/Write
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R
Register Description
System Control Register
Output Voltage Enable Register 1
Output Voltage Status Register 1
Output Voltage Enable Register 2
Output Voltage Status Register 2
Voltage Change Control Register 1
BUCK1 Target Voltage 1 Register
BUCK1 DVM Target Voltage 2 Register
V
CC
_APPS Voltage Ramp Control
Dummy Register
Dummy Register
LDO5 Target Voltage 1
LDO5 Target Voltage 2
LDO1 Target Voltage 1 Register
LDO1 Voltage 2 Register
LDO2 Voltage Control Registers
LDO3 & LDO4 Voltage Control Registers
System Control Register 1
System Control Register 2
Output Voltage Enable Register 3
Output Voltage Status Register 3
Output Voltage Enable Register 3
V
CC
_Buck2 Target Voltage
V
CC
_Buck3 Target Voltage
Buck 32 Voltage Ramp Control
Interrupt Status Register A
Backup Battery Charger Control Register
Internal 1 Revision Register
Internal 2 Revision Register
SERIAL INTERFACE REGISTER SELECTION CODES (Bold face voltages are default values)
System Control Status Register
Register is an 8 bit register which specifies the control bits for the PMIC clocks. This register works in conjunction with the SYNC
pin where an external clock PLL buffer operating at 13 MHz is synchronized with the oscillators of the buck converters.
System Control Register (SCR) 8h’07
Bit
Designation
Reset Value
7
6
5
4
3
2
1
0
Reserved
0
CLK_SCL
0
0
0
0
0
0
0
System Control Register (SCR) 8h’07 Definitions
Bit
7-1
0
Access
R/W
Name
CLK_SCL
Description
Reserved
External Clock Select
0 = Internal Oscillator clock for Buck Converters
1 = External 13 MHz Oscillator clock for Buck Converters
L
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