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參數(shù)資料
| 型號： | LP3972 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Power Management Unit for Advanced Application Processors |
| 中文描述： | 電源管理單元的高級應(yīng)用處理器 |
| 文件頁數(shù)： | 21/59頁 |
| 文件大小： | 1072K |
| 代理商： | LP3972 |
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I
2
C Compatible Interface
I
2
C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
20207614
I
2
C START and STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I
2
C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I
2
C master always
generates START and STOP bits. The I
2
C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I
2
C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
20207615
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte of data has to be followed by an
acknowledge bit. The acknowledge related clock pulse is
generated by the master. The transmitter releases the SDA
line (HIGH) during the acknowledge clock pulse. The re-
ceiver must pull down the SDA line during the 9th clock
pulse, signifying an acknowledge.Areceiver which has been
addressed must generate an acknowledge after each byte
has been received.
After the START condition, a chip address is sent by the I
2
C
master. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP3972 address
is 34h. For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
I
2
C CHIP ADDRESS - 7h’34
MSB
ADR6
Bit7
0
ADR5
Bit6
1
ADR4
Bit5
1
ADR3
Bit4
0
ADR2
Bit3
1
ADR1
Bit2
0
ADR0
Bit1
0
R/W
Bit0
R/W
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP3972_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Power Management Unit for Advanced Application Processors |
| LP3972SQ-0514/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3972SQ-5810/NOPB | 功能描述:監(jiān)控電路 Pwr Mgmt Unit RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| LP3972SQ-A413 | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3972SQ-A413/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
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