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參數(shù)資料
| 型號： | L6701TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3 Phase Controller for VR10, VR9 and K8 CPUs |
| 中文描述： | 3 VR10，VR9和K8處理器相控制器 |
| 文件頁數(shù)： | 30/44頁 |
| 文件大?。?/td> | 492K |
| 代理商： | L6701TR |
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13 Output voltage Monitor and Protections
L6701
30/44
Figure 13. Output Voltage Protections and typical principle connections
13.3 Over Voltage
Once VCC crosses the turn-ON threshold and the device is enabled (EN = Free), L6701
provides an Over Voltage Protection according to the DAC_SEL status: when the voltage
sensed by VSEN overcomes the OVP threshold, the controller permanently switches on all the
low-side MOSFETs and switches off all the high-side MOSFETs in order to protect the load.
The FAULT pin is driven high (5V) and power supply or EN pin cycling is required to restart
operations.
The OVP (and Pre-OVP) Threshold varies according to the operative mode selected as
reported in
Table 10
.
13.4 Feedback Disconnection
L6701 allows to monitor the output voltage in two different points:
Remotely, through the remote buffer, across VSEN
Locally across the CS- pin (negligibly offset by
●
●
).
By comparing the voltage present at these two different locations, L6701 is able to understand
if the output voltage feedback is connected. When CS- is more than 1V higher than VSEN,
(See
Figure 14
) the device stops switching with the low side MOSFETs permanently ON and
drives high the FAULT pin. The condition is latched until VCC or EN cycled.
Table 10.
OVP and Preliminary OVP Thresholds
DAC_SEL
Operative Mode
Pre-OVP
OVP
0
VR9
2.1
2.1
82k
to SGND
VR10
1.9
1.9
Open
K8
1.9
1.9
VCC
+12V
+5V
SB
Vcc
UVLO
OVP
UVLO
VCC
Preliminary OVP Enabled
FBR Monitored
No Protection
Provided
(EN = Free)
OVP Protection
VSEN Monitored
(EN = 0)
Preliminary OVP
FBR/DACSEL Monitor
R
D
I
CS
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