參數(shù)資料
型號(hào)： L6701TR
廠商： 意法半導(dǎo)體
英文描述： 3 Phase Controller for VR10, VR9 and K8 CPUs
中文描述： 3 VR10，VR9和K8處理器相控制器
文件頁(yè)數(shù)： 20/44頁(yè)
文件大?。?/td> 492K
代理商： L6701TR
9 Current Sharing Loop and Current Reading
L6701
20/44
9
Current Sharing Loop and Current Reading
9.1
Current Sharing Loop
L6701 embeds two separate Current Reading circuitries used to perform Current Sharing and
OCP through ISENx pins and Voltage Positioning (Droop Function) through CS+ and CS- pins
(See
Section 10
).
Current sharing control loop and connections are reported in
Figure 6
: the current read through
the I
SENx
pins is converted into a current I
INFOx
proportional to the current delivered by each
phase and the information about the average current I
AVG
=
Σ
I
INFOx
/ 3 is internally built into the
device. The error between the read current I
INFOx
and the reference I
AVG
is then converted into
a voltage that with a proper gain is used to adjust the duty cycle whose dominant value is set by
the voltage error amplifier in order to equalize the current carried by each phase.
9.2
Current Reading for Current Sharing
The current flowing trough each phase is read using the voltage drop across the low side
MOSFETs R
DS(on)
or across a sense resistor in its series and it is internally converted into a
current. The trans-conductance ratio is issued by the external resistor R
ISEN
placed outside the
chip between I
SENx
and the reading point (usually the LS MOSFET Drain).
The current sense circuit tracks the current information for a time T
TRACK
centered in the
middle of the LS conduction time and holds the tracked information during the rest of the
period. The current that flows from the I
SENx
pin is the current information used by the device to
perform current sharing and OCP and it is given by:
R
R
ISEN
where R
DS(on)
is the ON resistance of the low side MOSFET and R
ISEN
is the trans-
conductance resistor connected between the ISENx pins and the LS Drain; I
PHASEx
is the
current carried by the relative phase and I
INFOx
is the current information signal reproduced
internally. R
ISENx
is designed according to the Over Current Protection: see
Section 13.6
for
details.
Figure 6.
Current Sharing Loop and Current Reading Connections
I
ISENx
-----------------
I
PHASEx
I
INFOx
=
=
I
INFO1
PWM1 Out
From EA
I
INFO2
I
AVG
PWM2 Out
I
INFO3
PWM3 Out
AVG
ISENx
LGATEx
I
PHASEx
R
ISEN
I
ISENx
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