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參數(shù)資料
| 型號： | L6701TR |
| 廠商： | 意法半導體 |
| 英文描述： | 3 Phase Controller for VR10, VR9 and K8 CPUs |
| 中文描述： | 3 VR10，VR9和K8處理器相控制器 |
| 文件頁數(shù)： | 23/44頁 |
| 文件大小： | 492K |
| 代理商： | L6701TR |
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L6701
10 Output Voltage Positioning
23/44
and, multiplied by three, sourced by the FB pin (I
DROOP
). R
FB
gives the final gain to program
the desired load-line slope.
As before, the voltage positioning equations results (See
Figure 9
):
As a consequence:
=>
The device forces I
DROOP
= I
CS
x3, proportional to the read current, into the feedback resistor
R
FB
implementing the load regulation dependence. The output characteristic vs. load current is
then given by (Offset disabled):
Where R
LLDIFF
is the resulting differential load-line resistance implemented by the system. The
whole power supply can be then represented by a "real" voltage generator with an equivalent
output resistance R
LLDIFF
and a voltage value of VID.
R
FB
resistor can be then designed according to the Load-Line (R
LLDIFF
) specifications as
follow:
R
3
.
where R
D
is typically designed to have I
CS
= 35
μ
A at the maximum output current (OCP).
Table 9
contains a quick-reference guide to design applications with typical and/or differential
current sense.
Figure 9.
Fully Differential Load-Line Current-Reading (pat. pend.)
I
CS
I
OUT
+
s R
PH
C
1
PH
--------+
R
D
-------------
=
L
DCR
-------------
R
PH
C
PH
=
I
CS
I
OUT
DCR
R
D
-------------
=
V
OUT
VID
R
FB
I
DROOP
–
VID
3 R
FB
DCR
R
D
-------------
I
OUT
–
VID
R
LLDIFF
I
OUT
–
=
=
=
R
FB
---------------------
R
DCR
-------------
=
L2
L1
L3
DCR1
DCR2
DCR3
C
PH
R
P
R
P
R
P
R
D
PHASE3
PHASE2
PHASE1
V
OUT
I
CS
CS+
CS-
FB
I
DROOP
x 3
R
F
C
F
R
FB
COMP
Fully Differential Current Reading
for Load-Line
C
PH
C
PH
R
D
R
D
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