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參數(shù)資料
| 型號(hào)： | L6701TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3 Phase Controller for VR10, VR9 and K8 CPUs |
| 中文描述： | 3 VR10，VR9和K8處理器相控制器 |
| 文件頁數(shù)： | 25/44頁 |
| 文件大小： | 492K |
| 代理商： | L6701TR |
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L6701
10 Output Voltage Positioning
25/44
10.5 Maximum Duty Cycle limitation
To provide proper time for current-reading in order to equalize the current carried by each
phase, the device implements a duty-cycle limitation. This limitation is not fixed but it is linearly
variable with the current delivered to the load as follow:
0.80 T
SW
0.40 T
SW
Duty Cycle limitation is variable with the delivered current to provide fast load transient
response at light load as well as assuring robust over-current protection.
Figure 10
shows the maximum output voltage that the device is able to regulate considering the
T
ON
limitation imposed by the previous relationship. If the desired output characteristic crosses
the limited-T
ON
maximum output voltage, the output resulting voltage will start to drop after the
cross-point. In this case, the output voltage starts to decrease following the resulting
characteristic (dotted in
Figure 10
) until UVP is detected or anyway until I
ISENx
= 35
μ
A.
Figure 10. Maximum Duty Cycle limitation
T
ON max
)
I
ISENx
I
ISENx
0
μ
A
=
35
μ
A
=
=
V
OUT
0.40 V
IN
Maximum Output Voltage
0.80 V
IN
I
OCP
= 3 x I
OCPx
(I
ISENx
= 35
μ
A)
I
OUT
V
OUT
0.40 V
IN
Limited T
ON
0.80 V
IN
I
OCP
= 3 x I
OCPx
(I
ISENx
= 35
μ
A)
I
OUT
Desired output Char.
Resulting Output Char.
UVP Threshold
Limted-T
ON
Output Char.
Limted-T
ON
Output Char.
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