參數(shù)資料
型號(hào)： KSZ8842-16MVL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 55/141頁
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8842-16MVL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8842-16MVL
主要屬性： 2 個(gè)端口，100BASE-TX/10BASE-T
次要屬性： 8/16 位接口，LinkMD 線纜診斷
已供物品： 板
相關(guān)產(chǎn)品： 576-3270-ND - IC SWITCH ETH 2P 32BIT 128LQFP
576-3076-ND - IC MAC CTLR 2PORT ETH 100-LFBGA
KSZ8842-32MVL-ND - IC ETHERNET SW 2PORT BUS 128LQFP
576-2120-ND - IC ETHERNET SW 2PORT BUS 128LQFP
576-2119-ND - IC ETHERNET SW 2PORT BUS 128LQFP
其它名稱： 576-1635
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
20
M9999-102207-1.9
Ball Number
Ball Name
Type
Ball Function
This ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or
don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM).
C3
SWR
Ipd
Synchronous Write/Read
Write/Read signal for synchronous bus accesses. Write cycles when high and
Read cycles when low.
A2
AEN
Ipu
Address Enable
Address qualifier for the address decoding, active Low.
B2
WRN
Ipd
Write Strobe Not
Asynchronous write strobe, active Low.
A1
ADSN
Ipd
Address Strobe Not
For systems that require address latching, the rising edge of ADSN indicates the
latching moment of A15-A1 and AEN.
B1
PWRDN
Ipu
Full-chip power-down. Low = Power down; High or floating = Normal operation.
C1
RXP1
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)
C2
RXM1
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)
D1
TXP1
I/O
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)
D2
TXM1
I/O
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)
F2
RXM2
I/O
Port 2 physical receive (MDI) or transmit (MDIX) signal (- differential)
F1
RXP2
I/O
Port 2 physical receive (MDI)or transmit (MDIX) signal (+ differential)
G2
TXM2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (- differential)
G1
TXP2
I/O
Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential)
H2
TEST2
Ipu
Test input 2
For normal operation, left this ball open.
G3
ISET
O
Set physical transmits output current.
Pull-down this ball with a 3.01K 1% resistor to ground.
J1
X1
I
K1
X2
O
25MHz crystal or oscillator clock connection.
Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V
tolerant oscillator and X2 is a no connect.
Note: Clock requirement is
± 50ppm for either crystal or oscillator.
J2
RSTN
Ipu
Hardware reset ball (active Low). This reset input is required minimum of 10ms
low after stable supply voltage 3.3V.
K2
A15
I
Address 15
K3
A14
I
Address 14
J3
A13
I
Address 13
H3
A12
I
Address 12
K4
A11
I
Address 11
J4
A10
I
Address 10
H4
A9
I
Address 9
K5
A8
I
Address 8
J5
A7
I
Address 7
H5
A6
I
Address 6
K6
A5
I
Address 5
J6
A4
I
Address 4
H6
A3
I
Address 3
K7
A2
I
Address 2
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