參數(shù)資料
型號： KSZ8842-16MVL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 114/141頁
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8842-16MVL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8842-16MVL
主要屬性： 2 個(gè)端口，100BASE-TX/10BASE-T
次要屬性： 8/16 位接口，LinkMD 線纜診斷
已供物品： 板
相關(guān)產(chǎn)品： 576-3270-ND - IC SWITCH ETH 2P 32BIT 128LQFP
576-3076-ND - IC MAC CTLR 2PORT ETH 100-LFBGA
KSZ8842-32MVL-ND - IC ETHERNET SW 2PORT BUS 128LQFP
576-2120-ND - IC ETHERNET SW 2PORT BUS 128LQFP
576-2119-ND - IC ETHERNET SW 2PORT BUS 128LQFP
其它名稱： 576-1635
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
74
M9999-102207-1.9
Bit
Default
R/W
Description
10
1
RW
Aging Enable
1 = enable age function in the chip.
0 = disable age function in the chip.
9
0
RW
Fast Age Enable
1 = turn on fast age (800us).
8
0
RW
Aggressive Back-Off Enable
1 = enable more aggressive back off algorithm in half-duplex mode to enhance
performance. This is not an IEEE standard.
7-4
-
RW
Reserved
3
0x0
RW
Pass Flow Control Packet
1 = switch will not filter 802.1x “flow control” packets.
2-1
-
RW
Reserved
0
RW
Link Change Age
1 = link change from “l(fā)ink” to “no link” will cause fast aging (<800us) to age address
table faster. After an age cycle is complete, the age logic will return to normal (300 +
75 seconds).
Note: If any port is unplugged, all addresses will be automatically aged out.
Bank 32 Switch Global Control Register 2 (0x04): SGCR2
This register contains the global control for the switch function.
Bit
Default
R/W
Description
15
0
RW
802.1Q VLAN Enable
1 = 802.1Q VLAN mode is turned on. VLAN table must be set up before the operation.
0 = 802.1Q VLAN is disabled.
14
0
RW
IGMP Snoop Enable On Switch Host port
1 = IGMP snoop is enabled.
All the IGMP packets are forwarded to the Switch host port.
0 = IGMP snoop is disabled.
13
0
RW
Ipv6 MLD Snooping Enable
1 = enable IPv6 MLD snooping
12
0
RW
Ipv6 MLD Snooping Option
1 = enable IPv6 MLD snooping option
11
0
RW
Priority Scheme Select
0 = always TX higher priority packets first.
1 = Weighted Fair Queueing enabled. When all four queues have packets waiting to
transmit, the bandwidth allocation is q3:q2:q1:a0 = 8:4:2:1.
If any queues are empty, the highest non-empty queue gets one more weighting. For
example, if q2 is empty, q3:q1:q0 becomes (8+1): 0:2:1.
10-9
0x0
RW
Reserved
8
0
RW
Sniff Mode Select
1 =performs RX and TX sniff (both the source port and destination port need to
match).
0 = performs RX or TX sniff (either the source port or destination port needs to match).
This is the mode used to implement RX only sniff.
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