參數(shù)資料
型號： KSZ8842-16MVL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 53/141頁
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8842-16MVL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8842-16MVL
主要屬性： 2 個端口，100BASE-TX/10BASE-T
次要屬性： 8/16 位接口，LinkMD 線纜診斷
已供物品： 板
相關(guān)產(chǎn)品： 576-3270-ND - IC SWITCH ETH 2P 32BIT 128LQFP
576-3076-ND - IC MAC CTLR 2PORT ETH 100-LFBGA
KSZ8842-32MVL-ND - IC ETHERNET SW 2PORT BUS 128LQFP
576-2120-ND - IC ETHERNET SW 2PORT BUS 128LQFP
576-2119-ND - IC ETHERNET SW 2PORT BUS 128LQFP
其它名稱： 576-1635
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
19
M9999-102207-1.9
Ball Number
Ball Name
Type
Ball Function
This ball should be tied Low or unconnected if it is in asynchronous mode.
B8
SRDYN
Opu
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and VLBus-
like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This signal
is synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8842M drives this ball low to
signal wait states.
C8
INTRN
Opd
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set, this ball
need an external 4.7K pull-up resistor.
A7
LDEVN
Opd
Local Device Not
Active Low output signal, asserted when AEN is Low and A15-A4 decode to the
KSZ8842M address programmed into the high byte of the base address register.
LDEVN is a combinational decode of the Address and AEN signal.
B7
RDN
Ipd
Read Strobe Not
Asynchronous read strobe, active Low.
C7
EECS
Opu
EEPROM Chip Select
A6
ARDY
Opd
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus access
cycles. It is asynchronous to the host CPU or bus clock. This ball needs an
external 4.7K pull-up resistor.
B6
CYCLEN
Ipd
Cycle Not
For VLBus-like mode cycle signal; this ball follows the addressing cycle to signal
the command cycle.
For burst mode (32-bit interface only), this ball stays High for read cycles and
Low for write cycles.
C6
P2LED3
Opd
Port 2 LED indicator
See the description in balls A9, B9, and C9.
A5
VLBUSN
Ipd
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or
EISA-like burst mode.
B5
EEEN
Ipd
EEPROM Enable
EEPROM is enabled and connected when this ball is pull-up.
EEPROM is disabled when this ball is pull-down or no connect.
A4
P1LED3
Opd
Port 1 LED indicator
See the description in balls A10, B10, and C10.
B4
EEDO
Opd
EEPROM Data Out
This ball is connected to DI input of the serial EEPROM.
A3
EESK
Opd
EEPROM Serial Clock
A 4
s (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 800 ns (OBCR[1:0]=00
on-chip bus speed @ 125 MHz) serial output clock cycle to load configuration
data from the serial EEPROM.
B3
EEDI
Ipd
EEPROM Data In
This ball is connected to DO output of the serial EEPROM when EEEN is pull-
up.
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