參數(shù)資料
型號： KSZ8842-16MVL-EVAL
廠商： Micrel Inc
文件頁數(shù)： 118/141頁
文件大?。?/td> 0K
描述： BOARD EVALUATION KSZ8842-16MVL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng)控制器（PHY 和 MAC）
嵌入式： 否
已用 IC / 零件： KSZ8842-16MVL
主要屬性： 2 個端口，100BASE-TX/10BASE-T
次要屬性： 8/16 位接口，LinkMD 線纜診斷
已供物品： 板
相關(guān)產(chǎn)品： 576-3270-ND - IC SWITCH ETH 2P 32BIT 128LQFP
576-3076-ND - IC MAC CTLR 2PORT ETH 100-LFBGA
KSZ8842-32MVL-ND - IC ETHERNET SW 2PORT BUS 128LQFP
576-2120-ND - IC ETHERNET SW 2PORT BUS 128LQFP
576-2119-ND - IC ETHERNET SW 2PORT BUS 128LQFP
其它名稱： 576-1635
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
78
M9999-102207-1.9
Bank 33 Switch Global Control Register 6 (0x00): SGCR6
Bit
Default
R/W
Description
15-14
0x3
R/W
Tag_0x7
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its
IEEE Tag has a value of 0x7.
13-12
0x3
R/W
Tag_0x6
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its
IEEE Tag has a value of 0x6.
11-10
0x2
R/W
Tag_0x5
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its
IEEE Tag has a value of 0x5.
9-8
0x2
R/W
Tag_0x4
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its
IEEE Tag has a value of 0x4.
7-6
0x1
R/W
Tag_0x3
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its
IEEE Tag has a value of 0x3.
5-4
0x1
R/W
Tag_0x2
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its
IEEE Tag has a value of 0x2.
3-2
0x0
R/W
Tag_0x1
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its
IEEE Tag has a value of 0x1.
1-0
0x0
R/W
Tag_0x0
IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its
IEEE Tag has a value of 0x0.
Bank 33 Switch Global Control Register 7 (0x02): SGCR7
Bit
Default
R/W
Description
15-8
0x00
R/W
Reserved
7
0
R/W
Unknown Default Port Enable
Send packets with unknown destination address to specified ports in bits [2:0].
1 = enable to send unknown DA packet
6-3
-
R/W
Reserved
2-0
0x7
R/W
Unknown Packet Default Port(s)
Specify which ports to send packets with unknown destination addresses. Feature is
enabled by bit [7].
Bit 2 for the host port, bit 1 for port 2, and bit 0 for port 1
Banks 34 – 38: Reserved
Except Bank Select Register (0xE)
Bank 39 MAC Address Register 1 (0x00): MACAR1
This register contains the MAC address for the switch function. This MAC address is used for sending PAUSE frame.
Bit
Default
R/W
Description
15-0
0x0010
RW
MACA[47:32]
Specifies MAC address 1. This value has to be same as MARH in Bank2.
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