
KBE00F005A-D411
MCP MEMORY
June 2005
58
Revision 1.0
D. DEVICE OPERATIONS (continued)
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
t
RAS
(min) and "t
RP
" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same time
as burst read or burst write by asserting high on A10/AP. If burst
read or burst write by asserting high on A10/AP, the bank is left
active until a new command is asserted. Once auto precharge
command is given, no new commands are possible to that partic-
ular bank until the bank achieves idle state.
AUTO REFRESH
The storage cells of 64Mb, 128Mb and 256Mb SDRAM need to
be refreshed every 64ms to maintain data. An auto refresh cycle
accomplishes refresh of a single row of storage cells. The inter-
nal counter increments automatically on every auto refresh cycle
to refresh all the rows. An auto refresh command is issued by
asserting low on CS, RAS and CAS with high on CKE and WE.
The auto refresh command can only be asserted with all banks
being in idle state and the device is not in power down mode
(CKE is high in the previous cycle). The time required to com-
plete the auto refresh operation is specified by t
RC
(min). The min-
imum number of clock cycles required can be calculated by
driving t
RC
with clock cycle time and them rounding up to the next
higher integer. The auto refresh command must be followed by
NOP's until the auto refresh operation is completed. All banks will
be in the idle state at the end of auto refresh operation. The auto
refresh is the preferred refresh mode when the SDRAM is being
used for normal data transactions. The 64Mb and 128Mb
SDRAM’s auto refresh cycle can be performed once in 15.6us or
a burst of 4096 auto refresh cycles once in 64ms. The 256Mb
and 512Mb SDRAM’s auto refresh cycle can be performed once
in 7.8us or a burst of 8192 auto refresh cycles once in 64ms.
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are inter-
nally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE. Once
the self refresh mode is entered, only CKE state being low mat-
ters, all the other inputs including the clock are ignored in order to
remain in the self refresh mode.
The self refresh is exited by restarting the external clock and then
asserting high on CKE. This must be followed by NOP's for a
minimum time of tSRFX before the SDRAM reaches idle state to
begin normal operation. In case that the system uses burst auto
refresh during normal operation, it is recommended to use burst
8192 auto refresh cycles for 256Mb and 512Mb, and burst 4096
auto refresh cycles for 128Mb and 64Mb immediately before
entering self refresh mode and after exiting in self refresh mode.
On the other hand, if the system uses the distributed auto
refresh, the system only has to keep the refresh duty cycle.