參數(shù)資料
型號: KAB03D100M-TNGP
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: Multi-Chip Package MEMORY
中文描述: 多芯片封裝存儲器
文件頁數(shù): 50/72頁
文件大?。?/td> 1378K
代理商: KAB03D100M-TNGP
KAB0xD100M - TxGP
Revision 1.11
August 2003
- 50 -
MCP MEMORY
SEC Only
Alternate WE Controlled Program Operations
NOR Flash SWITCHING WAVEFORMS
NOTES:
1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
OE
Address
t
CS
CE
R
DATA
WE
t
AH
t
OH
t
DF
t
AS
t
RC
t
OE
t
CE
t
DS
t
DH
t
WP
t
OES
t
PGM
Status
DOUT
555H
PA
PA
A0H
Data Polling
t
CH
PD
t
WPH
R/B
R
t
BUSY
t
RB
t
WC
Parameter
Symbol
70ns
80ns
Unit
Min
Max
Min
Max
Write Cycle Time
t
WC
70
-
80
-
ns
Address Setup Time
t
AS
0
-
0
-
ns
Address Hold Time
t
AH
45
-
45
-
ns
Data Setup Time
t
DS
35
-
35
-
ns
Data Hold Time
t
DH
0
-
0
-
ns
CE
R
Setup Time
t
CS
0
-
0
-
ns
CE
R
Hold Time
t
CH
0
-
0
-
ns
OE Setup Time
t
OES
0
-
0
-
ns
Write Pulse Width
t
WP
35
-
35
-
ns
Write Pulse Width High
t
WPH
25
-
25
-
ns
Programming Operation
Word
t
PGM
14(typ.)
14(typ.)
us
Byte
9(typ.)
9(typ.)
us
Accelerated Programming Operation
Word
t
ACCPGM
9(typ.)
9(typ.)
μ
s
μ
s
Byte
7(typ.)
7(typ.)
Read Cycle Time
t
RC
70
-
80
-
ns
Chip Enable Access Time
t
CE
-
70
-
80
ns
Output Enable Time
t
OE
-
25
-
25
ns
CE
R
& OE Disable Time
t
DF
-
16
-
16
ns
Output Hold Time from Address, CE
R
or OE
t
OH
0
-
0
-
ns
Program/Erase Valide to R/B
R
Delay
t
BUSY
90
-
90
-
ns
Recovery Time from R/B
R
t
RB
0
-
0
-
ns
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KAB04D100M-TLGP 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Multi-Chip Package MEMORY
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