
FLASH MEMORY
8
K9K2G08U0A
Preliminary
CAPACITANCE
(
T
A
=25
°
C,
V
CC
=3.3V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
20
pF
Input Capacitance
C
IN
V
IN
=0V
-
20
pF
VALID BLOCK
NOTE
:
1. The
K9K2G08U0A
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
. Do not erase
or program factory-marked bad blocks.
Refer to the attached technical notes for appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction up to 1K Program/
Earase cycles..
AC TEST CONDITION
(K9K2G08U0A-VCB0 :TA=0 to 70
°
C, K9K2G08U0A-VIB0:TA=-40 to 85
°
C
K9K2G08U0A : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
2008
-
2048
Blocks
Parameter
K9K2G08U0A
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load (Vcc:3.3V +/-10%)
1 TTL GATE and CL=50pF
Program / Erase Characteristics
NOTE
: 1.Typical program time is defined as the time within which more than 50% of whole pages are programmed at Vcc of 3.3V and 25’C
2. Max. time of
t
CBSY
depends on timing between internal program completion and data in
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
*1
-
200
700
μ
s
Dummy Busy Time for Cache Program
t
CBSY
*2
3
700
μ
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
4
cycles
Spare Array
-
-
4
cycles
Block Erase Time
t
BERS
-
2
3
ms
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input(5clock)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input(5clock)
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
X
X
X
X
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
Stand-by