
FLASH MEMORY
29
K9K2G08U0A
Preliminary
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block.
Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed
into memory cell.
Figure 9. Random Data Input In a Page
80h
R/B
Address & Data Input
I/O
0
Pass
10h
70h
Fail
t
PROG
85h
Address & Data Input
After writing the first set of data up to 2112byte into the selected cache registers, Cache Program command (15h) instead of actual
Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer data from cache reg-
isters to data registers, the device remains in Busy state for a short period of time(tCBSY) and has its cache registers ready for the
next data-input while the internal programming gets started with the data loaded into data registers. Read Status command (70h) may
be issued to find out when cache registers become ready by polling the Cache-Busy status bit(I/O 6). Pass/fail status of only the pre-
viouse page is available upon the return to Ready state. When the next set of data is inputted with the Cache Program command,
tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only when the
pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/
O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of
programming only with R/B, the last page of the target programming sequence must be progammed with actual Page Program com-
mand (10h). If the Cache Program command (15h) is used instead, status bit (I/O5) must be polled to find out when the last program-
ming is actually finished before starting other operations such as read. Pass/fail status is available in two steps. I/O 1 returns with the
status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O 0 with the status of current page upon true
Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may be read together when I/O 0 is checked.
Figure 10. Cache Program
(available only within a block)
t
CBSY
80h
R/B
80h
Address &
Data Input
15h
80h
Address &
Data Input
15h
80h
Address &
Data Input
10h
t
CBSY
t
CBSY
t
PROG
70h
Address &
Data Input*
15h
80h
R/B
70h
t
CBSY
Address &
Data Input
Col Add1,2 & Row Add1,2,3
Data
15h
Status
80h
70h
t
CBSY
Address &
Data Input
Col Add1,2 & Row Add1,2,3
Data
15h
Status
80h
t
CBSY
Address &
Data Input
Col Add1,2 & Row Add1,2,3
Data
15h
80h
t
CBSY
Address &
Data Input
Col Add1,2 & Row Add1,2,3
Data
15h
70h
Status
output
70h
Status
output
Check I/O5 for internal ready/busy
Check I/O0,1 for pass/fail
Check I/O1 for pass/fail
I/Ox
I/Ox
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
"0"
"1"