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參數(shù)資料
| 型號： | K7B403625M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36-Bit Synchronous Burst SRAM |
| 中文描述： | 128K × 36至位同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 439K |
| 代理商： | K7B403625M |
K7B403625M
128Kx36 Synchronous SRAM
- 8 -
Rev 2.0
December 1998
AC TIMING CHARACTERISTICS
(T
A
=0 to 70
°
C, V
DD
=3.3V+0.3V/-0.165V)
Notes :
1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
4. At any given voltage and temperature, t
HZC
is less than t
LZC.
PARAMETER
SYMBOL
-75
-80
-90
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Cycle Time
t
CYC
8.5
-
10
-
12
-
ns
Clock Access Time
t
CD
-
7.5
-
8
-
9
ns
Output Enable to Data Valid
t
OE
-
3.5
-
3.5
-
3.5
ns
Clock High to Output Low-Z
t
LZC
0
-
0
-
0
-
ns
Output Hold from Clock High
t
OH
2
-
2
-
2
-
ns
Output Enable Low to Output Low-Z
t
LZOE
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
t
HZOE
-
3.5
-
3.5
-
3.5
ns
Clock High to Output High-Z
t
HZC
2
3.5
2
3.5
2
3.5
ns
Clock High Pulse Width
t
CH
3
-
4
-
4.5
-
ns
Clock Low Pulse Width
t
CL
3
-
4
-
4.5
-
ns
Address Setup to Clock High
t
AS
2.0
-
2.0
-
2.0
-
ns
Address Status Setup to Clock High
t
SS
2.0
-
2.0
-
2.0
-
ns
Data Setup to Clock High
t
DS
2.0
-
2.0
-
2.0
-
ns
Write Setup to Clock High(GW, BW, WEx)
t
WS
2.0
-
2.0
-
2.0
-
ns
Address Advance Setup to Clock High
t
ADVS
2.0
-
2.0
-
2.0
-
ns
Chip Select Setup to Clock High
t
CSS
2.0
-
2.0
-
2.0
-
ns
Address Hold from Clock High
t
AH
0.5
-
0.5
-
0.5
-
ns
Address Status Hold from Clock High
t
SH
0.5
-
0.5
-
0.5
-
ns
Data Hold from Clock High
t
DH
0.5
-
0.5
-
0.5
-
ns
Write Hold from Clock High(GW, BW, WEx)
t
WH
0.5
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High
t
ADVH
0.5
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
t
CSH
0.5
-
0.5
-
0.5
-
ns
ZZ High to Power Down
t
PDS
2
-
2
-
2
-
cycle
ZZ Low to Power Up
t
PUS
2
-
2
-
2
-
cycle
Output Load(B)
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
5pF*
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Z0=50
* Capacitive Load consists of all components of
the test environment.
30pF*
RL=50
353
/
1538
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319
/
1667
VL=1.5V for 3.3V I/O
V
DDQ
/2 for 2.5V I/O
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