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參數(shù)資料
| 型號： | K7B403625M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36-Bit Synchronous Burst SRAM |
| 中文描述： | 128K × 36至位同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 439K |
| 代理商： | K7B403625M |
K7B403625M
128Kx36 Synchronous SRAM
- 1 -
Rev 2.0
December 1998
Document Title
128Kx36-Bit Synchronous Burst SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
0.3
1.0
2.0
History
Initial draft
Modify power down cycle timing & Interleaved read timing,
Insert Note 4 at AC timing characteristics.
Change I
SB1
value from 10mA to 30mA.
Change I
SB2
value from 10mA to 20mA.
Change Undershoot spec
from -3.0V(pulse width
≤
20ns) to -2.0V(pulse width
≤
t
CYC
/2)
Add Overshoot spec 4.6V((pulse width
≤
t
CYC
/2)
Change V
IH
max from 5.5V to V
DD
+0.5V
Change I
SB2
value from 20mA to 30mA.
Change V
DD
condition from V
DD
=3.3V+10%/-5% to V
DD
=3.3V+0.3V/-0.165V.
Final spec Release
Add V
DDQ
Supply voltage( 2.5V )
Draft Date
May. 15. 1997
Feb. 11. 1998
April. 14. 1998
May. 13. 1998
May. 15. 1998
Dec. 02. 1998
Remark
Preliminary
Preliminary
Preliminary
Preliminary
Final
Final
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