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參數(shù)資料
| 型號(hào)： | K7B403625M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Kx36-Bit Synchronous Burst SRAM |
| 中文描述： | 128K × 36至位同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 439K |
| 代理商： | K7B403625M |
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K7B403625M
128Kx36 Synchronous SRAM
- 2 -
Rev 2.0
December 1998
WEc
WEd
FAST ACCESS TIMES
PARAMETER
Symbol
-75
-80
-90
Unit
Cycle Time
t
CYC
8.5
10
12
ns
Clock Access Time
t
CD
7.5
8
9
ns
Output Enable Access Time
t
OE
3.5
3.5
3.5
ns
128Kx36-Bit Synchronous Burst SRAM
The K7B403625M is 4,718,592 bits Synchronous Static Ran-
dom Access Memory designed to support zero wait state per-
formance for advanced Pentium/Power PC based system. And
with CS
1
high, ADSP is blocked to control signals.
It can be organized as 128K words of 36 bits. And it integrates
address and control registers, a 2-bit burst address counter and
high output drive circuitry onto a single integrated circuit for
reduced components counts implementation of high perfor-
mance cache RAM applications.
Write cycles are internally self-timed and synchronous.
The self-timed write feature eliminates complex off chip write
pulse shaping logic, simplifying the cache design and further
reducing the component count.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′
s burst sequence and are controlled by the burst
address advance(ADV) input.
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B403625M is implemented with SAMSUNG
′
s high per-
formance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
GENERAL DESCRIPTION
FEATURES
Synchronous Operation.
On-Chip Address Counter.
Write Self-Timed Cycle.
On-Chip Address and Control Registers.
V
DD
= 3.3V+0.3V/-0.165V Power Supply.
V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
5V Tolerant Inputs except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
Three Chip Enables for simple depth expansion with No Data
Contention.
TTL-Level Three-State Output.
100-TQFP-1420A
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEa
OE
ZZ
DQa
0
~ DQd
7
DQPa ~ DQPd
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
128Kx36
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
OUTPUT
BUFFER
DATA-IN
REGISTER
C
R
C
R
A
′
0
~A
′
1
A
0
~A
1
A
2
~A
16
A
0
~A
16
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| K7D321874A-HC33 | 32Mb A-die DDR SRAM Specification |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7B403625M-QC75 | 制造商:Samsung Semiconductor 功能描述: |
| K7B403625M-QC90 | 制造商:Samsung Semiconductor 功能描述: |
| K7B801825B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18 Synchronous SRAM |
| K7B801825B-PC75000 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| K7B801825B-QC65 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM |
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