參數資料
| 型號： | ISLA118P50IRZ |
| 廠商： | Intersil |
| 文件頁數： | 32/34頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 產品培訓模塊： | Solutions for Test and Measurement Equipment |
| 標準包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數： | 8 |
| 采樣率（每秒）： | 500M |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 2 |
| 功率耗散（最大）： | 477mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數目和類型： | 2 個單端，單極；1 個差分，單極 |
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ISLA118P50
7
FN7565.2
July 25, 2011
Spurious-Free Dynamic Range (Notes 11, 12)
SFDR
fIN = 10MHz
68
dBc
fIN = 105MHz
63.5
68
dBc
fIN = 190MHz
68
dBc
fIN = 364MHz
67
dBc
fIN = 495MHz
67
dBc
fIN = 605MHz
63
dBc
fIN = 995MHz
48
dBc
Intermodulation Distortion
IMD
fIN = 70MHz
80
dBc
fIN = 170MHz
80
dBc
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
1.15
GHz
I2E SPECIFICATIONS
Offset mismatch-induced spurious power
No I2E Calibration performed
-70
dBFS
Active Run state enabled
-81
dBFS
I2E Settling Times
I2Epost_t
Calibration settling time for Active Run
state
1000
ms
Minimum Duration of Valid Analog Input
(Note 13)
tTE
Allow one I2E iteration of Offset, Gain
and Phase correction
500
s
Largest Interleave Spur
fIN = 10MHz to 240MHz, Active Run
State enabled, in Track Mode
-94
dBc
fIN = 10MHz to 240MHz, Active Run
State enabled and previously settled, in
Hold Mode
-82
dBc
fIN = 260MHz to 490MHz, Active Run
State enabled, in Track Mode
-89
dBc
fIN = 260MHz to 490MHz, Active Run
State enabled and previously settled, in
Hold Mode
-79
dBc
Total Interleave Spurious Power
Active Run State enabled, in Track
Mode, fIN is a broadband signal in the
1st Nyquist zone
-90
dBc
Active Run State enabled, in Track
Mode, fIN is a broadband signal in the
2nd Nyquist zone
-85
dBc
Sample Time Mismatch Between Unit A/Ds
Active Run State enabled, in Track Mode
30
fs
Gain Mismatch Between Unit A/Ds
0.01
%
Offset Mismatch Between Unit A/Ds
1mV
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.
8. See “Nap/Sleep” for more detail.
9. AC Specifications apply after internal calibration of the A/D is invoked at the given sample rate and temperature. Refer to “Power-On Calibration” and
“User Initiated Reset” for more detail.
10. The DLL Range setting must be changed for low speed operation.
11. The offset mismatch-induced spur energy, which occurs at fSAMPLE/2, is not included in any specification unless otherwise noted.
12. This specification only applies when I2E is in Active Run state, and in Track Mode.
13. Limits are specified over the full operating temperature and voltage range and are established by characterization and not production tested.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, FIN =105MHz, fSAMPLE = 500MSPS, after completion of I2E calibration. (Continued)
PARAMETER
SYMBOL
CONDITIONS
ISLA118P50
(Note 6)
UNITS
MIN
TYP
MAX
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