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| 型號： | ISLA118P50IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 18/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Test and Measurement Equipment |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 477mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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ISLA118P50
25
FN7565.2
July 25, 2011
by the I2E algorithm to update its sample time skew estimate.
Under such circumstances, I2E enters Hold state. In the Hold
state, the analog adjustments will be frozen and mismatch
estimate calculations will cease until such time as the analog
input achieves sufficient quality to allow the I2E algorithm to
make mismatch estimates again.
These registers allow the programming of the thresholds of the
meters used to determine the quality of the input signal. This can
be used by the application to optimize I2E’s behavior based on
knowledge of the input signal. For example, if a specific
application had an input signal that was typically 30dB down
from full scale, and was primarily concerned about analog
performance of the A/D at this input power, lowering the RMS
power threshold would allow I2E to continue tracking with this
input power level, thus allowing it to track over voltage and
temperature changes.
0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold
This 16-bit quantity is the RMS power threshold at which I2E will
enter Hold state. The RMS power of the analog input is calculated
continuously by I2E on incoming data.
A 12-bit number squared produces a 24-bit result (for A/D
resolutions under 12-bits, the A/D samples are MSB-aligned to
12-bit data). A dynamic number of these 24-bit results are
averaged to compare with this threshold approximately every
1s to decide whether or not to freeze I2E. The 24-bit threshold is
constructed with bits 23 through 20 (MSBs) assigned to 0, bits
19 through 4 assigned to this 16-bit quantity, and bits 3 through
0 (LSBs) assigned to 0. As an example, if the application wanted
to set this threshold to trigger near the RMS analog input of a
-20dBFS sinusoidal input, the calculation to determine this
register’s value would be
Therefore, programming 0x1488 into these two registers will
cause I2E to freeze when the signal being digitized has less RMS
power than a -20dBFS sinusoid.
The default value of this register is 0x1000, causing I2E to freeze
when the input amplitude is less than -21.2 dBFS.
The freezing of I2E by the RMS power meter threshold affects the
gain and sample time skew interleave mismatch estimates, but
not the offset mismatch estimate.
0x52 RMS Power Hysteresis
In order to prevent I2E from constantly oscillating between the
Hold and Track state, there is hysteresis in the comparison
described above. After I2E enters a frozen state, the RMS input
power must achieve
≥ threshold value + hysteresis to again
enter the old. The hysteresis quantity is a 24-bit value,
constructed with bits 23 through 12 (MSBs) being assigned to
0, bits 11 through 4 assigned to this register’s value, and bits 3
through 0 (LSBs) assigned to 0.
AC RMS Power Threshold
Similar to RMS power threshold, there must be sufficient AC RMS
power (or dV/dt) of the input signal to measure sample time
skew mismatch for an arbitrary input. This is clear from
observing the effect when a high voltage (and therefore large
RMS value) DC input is applied to the A/D input. Without
sufficient dV/dt in the input signal, no information about the
sample time skew between the core A/Ds can be determined
from the digitized samples. The AC RMS Power Meter is
implemented as a high-passed (via DSP) RMS power meter.
The writing of the AC RMS Power Threshold is different than
other SPI registers, and these registers are not listed in the SPI
memory map table. The required algorithm is documented
below.
1. Write the value 0x80 to the Index Register (SPI address 0x10)
2. Write the MSBs of the 16-bit quantity to SPI Address 0x150
3. Write the LSBs of the 16-bit quantity to SPI Address 0x14F
A 12-bit number squared produces a 24-bit result (for A/D
resolutions under 12-bits, the A/D samples are MSB-aligned to
12-bit data). A dynamic number of these 24-bit results are
averaged to compare with this threshold approximately every
1s to decide whether or not to freeze I2E. The 24-bit threshold is
constructed with bits 23 through 20 (MSBs) assigned to 0, bits
19 through 4 assigned to this 16-bit quantity, and bits 3 through
0 (LSBs) assigned to 0. The calculation methodology to set this
register is identical to the description in the RMS power threshold
description.
The freezing of I2E when the AC RMS power meter threshold is
not met affects the sample time skew interleave mismatch
estimate, but not the offset or gain mismatch estimates.
0x55 AC RMS Power Hysteresis
In order to prevent I2E from constantly oscillating between the
Hold and Track state, there is hysteresis in the comparison
described above. After I2E enters a frozen state, the AC RMS
input power must achieve
≥ threshold value + hysteresis to again
enter the Track state. The hysteresis quantity is a 24-bit value,
constructed with bits 23 through 12 (MSBs) being assigned to 0,
bits 11 through 4 assigned to this register’s value, and bits 3
through 0 (LSBs) assigned to 0.
ADDRESS 0X60-0X64: I2E INITIALIZATION
These registers provide access to the initialization values for
each of offset, gain, and sample time skew that I2E programs
into the target core A/D before adjusting to minimize interleave
mismatch. They can be used by the system to, for example,
reduce the convergence time of the I2E algorithm by
programming in the optimal values before turning I2E on. In
this case, I2E only needs to adjust for temperature and
voltage-induced changes since the optimal values were recorded.
RMScodes
2
-------
10
20
–
20
----------
×
2
12
290codes
×
=
(EQ. 2)
hex 290
2
()
0x014884TruncateMSBandLSBhexdigit
0x1488
=
d
=
(EQ. 3)
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