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參數(shù)資料
| 型號： | ISLA118P50IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/34頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 產(chǎn)品培訓模塊： | Solutions for Test and Measurement Equipment |
| 標準包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 477mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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ISLA118P50
23
FN7565.2
July 25, 2011
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. In
3-wire SPI mode, the burst is ended by pulling the CSB pin high. If
the device is operated in 2-wire mode the CSB pin is not
available. In that case, setting the burst_end address determines
the end of the transfer. During a write operation, the user must
be cautious to transmit the correct number of bytes based on the
starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A
Bits 1:0 ADC01, ADC00
Determines which A/D is addressed. Valid states for this
register are 0x01 or 0x10. The two A/D cores cannot be
adjusted concurrently.
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil A/D products.
Certain configuration commands (identified as Indexed in the SPI
map) can be executed on a per-converter basis. This register
determines which converter is being addressed for an Indexed
command. It is important to note that only a single converter can
be addressed at a time.
This register defaults to 00h, indicating that no A/D is addressed.
Error code ‘AD’ is returned if any indexed register is read from
without properly setting device_index_A.
ADDRESS 0X20: OFFSET_COARSE
ADDRESS 0X21: OFFSET_FINE
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 6. The data format is twos complement.
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’
-4.2% and ‘1100’ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%, -
2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 23h and 24h.
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
TABLE 5. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
TABLE 6. OFFSET ADJUSTMENTS
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
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